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Better handling of mapping to case in VHDL

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use others clause when possible, only convert to case
when it's a full case
This commit is contained in:
Jan Decaluwe 2010-10-08 18:21:45 +02:00
parent 869b7db239
commit db012cc557
2 changed files with 15 additions and 7 deletions
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2
myhdl/conversion/_analyze.py
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@ -1103,7 +1103,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
node.isCase = True node.isCase = True
node.caseVar = var1 node.caseVar = var1
node.caseItem = item1 node.caseItem = item1
if (len(choices) == _getNritems(var1.obj)) or (node.else_ is not None): if (len(choices) == _getNritems(var1.obj)) or node.else_:
node.isFullCase = True node.isFullCase = True

20
myhdl/conversion/_toVHDL.py
View File

@ -1614,7 +1614,8 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
def visit_If(self, node): def visit_If(self, node):
if node.ignore: if node.ignore:
return return
if node.isCase: # only map to VHDL case if it's a full case
if node.isFullCase:
self.mapToCase(node) self.mapToCase(node)
else: else:
self.mapToIf(node) self.mapToIf(node)
@ -1653,15 +1654,22 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.visit(var) self.visit(var)
self.write(" is") self.write(" is")
self.indent() self.indent()
for test, suite in node.tests: for i, (test, suite) in enumerate(node.tests):
self.writeline() self.writeline()
item = test.case[1] item = test.case[1]
self.write("when ")
if isinstance(item, EnumItemType): if isinstance(item, EnumItemType):
self.write(item._toVHDL()) itemRepr = item._toVHDL()
else: else:
self.write(self.BitRepr(item, obj)) itemRepr = self.BitRepr(item, obj)
self.write(" =>") comment = ""
# potentially use default clause for last test
if (i == len(node.tests)-1) and not node.else_:
self.write("when others")
comment = " -- %s" % itemRepr
else:
self.write("when ")
self.write(itemRepr)
self.write(" =>%s" % comment)
self.indent() self.indent()
self.visit_stmt(suite) self.visit_stmt(suite)
self.dedent() self.dedent()