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clean up setup.py
* Prefer setuptools over distutils * Extend version checking to disallow python 3.0 to 3.3 * Add python version classifiers
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setup.py
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setup.py
@ -1,48 +1,41 @@
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""" myhdl's distutils distribution and installation script. """
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""" myhdl's distribution and installation script. """
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from __future__ import print_function
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import sys
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requiredVersion = (2, 6)
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requiredVersionStr = ".".join([str(i) for i in requiredVersion])
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if sys.version_info < (2, 6) or (3, 0) <= sys.version_info < (3, 4):
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raise RuntimeError("Python version 2.6, 2.7 or >= 3.4 required.")
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versionError = "ERROR: myhdl requires Python %s or higher" % requiredVersionStr
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# use version_info to check version
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# this was new in 2.0, so first see if it exists
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# Prefer setuptools over distutils
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try:
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sys.version_info
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except:
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print(versionError)
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raise SystemExit(1)
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from setuptools import setup
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except ImportError:
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from distutils.core import setup
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if sys.version_info < requiredVersion:
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print(versionError)
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raise SystemExit(1)
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from distutils.core import setup
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classifiers = """\
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Development Status :: 5 - Production/Stable
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Intended Audience :: Developers
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License :: OSI Approved :: GNU Library or Lesser General Public License (LGPL)
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Operating System :: OS Independent
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Programming Language :: Python
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Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
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"""
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setup(name="myhdl",
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version="0.9",
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description="Python as a Hardware Description Language",
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long_description = "See home page.",
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author="Jan Decaluwe",
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author_email="jan@jandecaluwe.com",
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url="http://www.myhdl.org",
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download_url="https://bitbucket.org/jandecaluwe/myhdl/get/0.8.1.zip",
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packages=['myhdl', 'myhdl.conversion'],
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license="LGPL",
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platforms=["Any"],
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keywords="HDL ASIC FPGA hardware design",
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classifiers=filter(None, classifiers.split("\n")),
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)
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setup(
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name="myhdl",
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version="0.9.dev0",
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description="Python as a Hardware Description Language",
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long_description="See home page.",
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author="Jan Decaluwe",
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author_email="jan@jandecaluwe.com",
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url="http://www.myhdl.org",
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download_url="https://bitbucket.org/jandecaluwe/myhdl/get/0.8.1.zip",
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packages=['myhdl', 'myhdl.conversion'],
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license="LGPL",
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platforms='any',
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keywords="HDL ASIC FPGA hardware design",
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classifiers=[
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'Development Status :: 5 - Production/Stable',
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'Intended Audience :: Developers',
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'Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)',
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'License :: OSI Approved :: GNU Lesser General Public License v2 (LGPLv2)',
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'Operating System :: OS Independent',
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'Programming Language :: Python',
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'Programming Language :: Python :: 2',
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'Programming Language :: Python :: 2.6',
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'Programming Language :: Python :: 2.7',
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'Programming Language :: Python :: 3',
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'Programming Language :: Python :: 3.4',
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]
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)
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