From dc4eed5f90cb9f244bea610b1fa35defffa1243f Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Mon, 21 Feb 2005 21:47:27 +0000
Subject: [PATCH] optimize singleton sensitivity list in always_comb

---
 myhdl/_Simulation.py           |  5 +-
 myhdl/_always_comb.py          |  2 +
 myhdl/test/test_always_comb.py | 93 +++++++++++++++++++++++++++++++---
 3 files changed, 93 insertions(+), 7 deletions(-)

diff --git a/myhdl/_Simulation.py b/myhdl/_Simulation.py
index b78f4056..80efa04e 100644
--- a/myhdl/_Simulation.py
+++ b/myhdl/_Simulation.py
@@ -207,7 +207,10 @@ def _checkArgs(arglist):
         if isinstance(arg, GeneratorType):
             waiters.append(_inferWaiter(arg))
         elif isinstance(arg, _AlwaysComb):
-            waiters.append(_SignalTupleWaiter(arg.gen))
+            if isinstance(arg.senslist, tuple):
+                waiters.append(_SignalTupleWaiter(arg.gen))
+            else:
+                waiters.append(_SignalWaiter(arg.gen))
         elif isinstance(arg, Cosimulation):
             if cosim is not None:
                 raise SimulationError(_error.MultipleCosim)
diff --git a/myhdl/_always_comb.py b/myhdl/_always_comb.py
index a9042dc8..55990676 100644
--- a/myhdl/_always_comb.py
+++ b/myhdl/_always_comb.py
@@ -168,6 +168,8 @@ class _AlwaysComb(object):
         self.inputs = v.inputs
         self.outputs = v.outputs
         self.senslist = tuple([self.sigdict[n] for n in self.inputs])
+        if len(self.senslist) == 1:
+            self.senslist = self.senslist[0]
         self.gen = self.genfunc()
 
     def genfunc(self):
diff --git a/myhdl/test/test_always_comb.py b/myhdl/test/test_always_comb.py
index f369fdff..5f84c96a 100644
--- a/myhdl/test/test_always_comb.py
+++ b/myhdl/test/test_always_comb.py
@@ -25,7 +25,7 @@ __date__ = "$Date$"
 
 import random
 from random import randrange
-random.seed(1) # random, but deterministic
+# random.seed(3) # random, but deterministic
 
 import unittest
 from unittest import TestCase
@@ -33,7 +33,7 @@ import inspect
 from sets import Set
 
 from myhdl import Signal, Simulation, instances, processes, \
-                  intbv, posedge, negedge, delay, StopSimulation
+                  intbv, posedge, negedge, delay, StopSimulation, now
 
 from myhdl._always_comb import always_comb, _AlwaysComb, \
                                AlwaysCombError, _error
@@ -212,7 +212,7 @@ class AlwaysCombCompilationTest(TestCase):
             self.fail()
 
 
-class AlwaysCombSimulationTest(TestCase):
+class AlwaysCombSimulationTest1(TestCase):
 
     def bench(self, function):
 
@@ -222,16 +222,16 @@ class AlwaysCombSimulationTest(TestCase):
         c = Signal(0)
         d = Signal(0)
         z = Signal(0)
-        vectors = [intbv(j) for i in range(8) for j in range(16)]
+        vectors = [intbv(j) for i in range(32) for j in range(16)]
         random.shuffle(vectors)
 
         
-        def combfunc():
+        def combFunc():
             if __debug__:
                 f = x
             x.next = function(a, b, c, d)
 
-        comb = always_comb(combfunc)
+        comb = always_comb(combFunc)
 
         def clkGen():
             while 1:
@@ -285,6 +285,87 @@ class AlwaysCombSimulationTest(TestCase):
             return not (a & (not b)) | ((not c) & d)
         Simulation(self.bench(function)).run(quiet=QUIET)
 
+        
+class AlwaysCombSimulationTest2(TestCase):
+
+    def bench(self, funcName="and"):
+
+        clk = Signal(0)
+        a = Signal(0)
+        b = Signal(0)
+        c = Signal(0)
+        d = Signal(0)
+        k = Signal(0)
+        z = Signal(0)
+        x = Signal(0)
+        vectors = [intbv(j) for i in range(32) for j in range(16)]
+        random.shuffle(vectors)
+
+        def andFunc():
+            x.next = a & b & c & d
+        def andGenFunc():
+            while 1:
+                z.next =  a & b & c & d
+                yield a, b, c, d
+            
+        def orFunc():
+            x.next = a | b | c | d
+        def orGenFunc():
+            while 1:
+                z.next = a | b | c | d
+                yield a, b, c, d
+            
+        def logicFunc():
+            x.next = not (a & (not b)) | ((not c) & d)
+        def logicGenFunc():
+            while 1:
+                z.next = not (a & (not b)) | ((not c) & d)
+                yield a, b, c, d
+
+        def incFunc():
+            x.next = k + 1
+        def incGenFunc():
+            while 1:
+                z.next = k + 1
+                yield k
+       
+        combFunc = eval(funcName + "Func")
+        comb = always_comb(combFunc)
+        genFunc = eval(funcName + "GenFunc")
+        gen = genFunc()
+
+        def clkGen():
+            while 1:
+                yield delay(10)
+                clk.next ^= 1
+
+        def stimulus():
+            for v in vectors:
+                a.next = v[0]
+                b.next = v[1]
+                c.next = v[2]
+                d.next = v[3]
+                k.next = v
+                yield posedge(clk)
+                yield negedge(clk)
+                self.assertEqual(x, z)
+            raise StopSimulation, "always_comb simulation test"
+
+        return comb, gen, clkGen(), stimulus()
+        
+
+    def testAnd(self):
+        Simulation(self.bench("and")).run(quiet=QUIET)
+        
+    def testOr(self):
+        Simulation(self.bench("or")).run(quiet=QUIET)
+        
+    def testLogic(self):
+        Simulation(self.bench("logic")).run(quiet=QUIET)
+        
+    def testInc(self):
+        Simulation(self.bench("inc")).run(quiet=QUIET)
+
 
 if __name__ == "__main__":
     unittest.main()