diff --git a/myhdl/_Simulation.py b/myhdl/_Simulation.py
index 1f4f1760..f0e9e4e9 100644
--- a/myhdl/_Simulation.py
+++ b/myhdl/_Simulation.py
@@ -211,6 +211,7 @@ def _checkArgs(arglist):
             if cosim is not None:
                 raise MultipleCosimError
             cosim = arg
+            waiters.append(_Waiter(cosim._waiter()))
         else:
             raise ArgTypeError(str(type(arg)))
     return waiters, cosim
diff --git a/myhdl/test/toVerilog/test_NotSupported.py b/myhdl/test/toVerilog/test_NotSupported.py
index 6c82bed8..dd83bfcb 100644
--- a/myhdl/test/toVerilog/test_NotSupported.py
+++ b/myhdl/test/toVerilog/test_NotSupported.py
@@ -3,14 +3,14 @@ path = os.path
 import unittest
 
 from myhdl import *
-from myhdl._toVerilog import Error, _error
+from myhdl._toVerilog import ToVerilogError, _error
 
 class TestNotSupported(unittest.TestCase):
     
     def check(self, *args):
         try:
             i = toVerilog(*args)
-        except Error, e:
+        except ToVerilogError, e:
             self.assertEqual(e.kind, _error.NotSupported)
         except:
             self.fail()
diff --git a/myhdl/test/toVerilog/test_bin2gray.py b/myhdl/test/toVerilog/test_bin2gray.py
index 7edc4419..f9fc4ff6 100644
--- a/myhdl/test/toVerilog/test_bin2gray.py
+++ b/myhdl/test/toVerilog/test_bin2gray.py
@@ -47,7 +47,7 @@ class TestBin2Gray(TestCase):
                 yield delay(10)
                 #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
                 #print bin(G, width)
-                print bin(G_v, width)
+                #print bin(G_v, width)
                 self.assertEqual(G, G_v)
 
         return bin2gray_v_inst, stimulus(), bin2gray_inst