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checkArgs bug

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This commit is contained in:
jand 2003-11-16 15:20:27 +00:00
parent 9720743a21
commit dd8968df9a
3 changed files with 4 additions and 3 deletions
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1
myhdl/_Simulation.py
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@ -211,6 +211,7 @@ def _checkArgs(arglist):
if cosim is not None: if cosim is not None:
raise MultipleCosimError raise MultipleCosimError
cosim = arg cosim = arg
waiters.append(_Waiter(cosim._waiter()))
else: else:
raise ArgTypeError(str(type(arg))) raise ArgTypeError(str(type(arg)))
return waiters, cosim return waiters, cosim

4
myhdl/test/toVerilog/test_NotSupported.py
View File

@ -3,14 +3,14 @@ path = os.path
import unittest import unittest
from myhdl import * from myhdl import *
from myhdl._toVerilog import Error, _error from myhdl._toVerilog import ToVerilogError, _error
class TestNotSupported(unittest.TestCase): class TestNotSupported(unittest.TestCase):
def check(self, *args): def check(self, *args):
try: try:
i = toVerilog(*args) i = toVerilog(*args)
except Error, e: except ToVerilogError, e:
self.assertEqual(e.kind, _error.NotSupported) self.assertEqual(e.kind, _error.NotSupported)
except: except:
self.fail() self.fail()

2
myhdl/test/toVerilog/test_bin2gray.py
View File

@ -47,7 +47,7 @@ class TestBin2Gray(TestCase):
yield delay(10) yield delay(10)
#print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width) #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
#print bin(G, width) #print bin(G, width)
print bin(G_v, width) #print bin(G_v, width)
self.assertEqual(G, G_v) self.assertEqual(G, G_v)
return bin2gray_v_inst, stimulus(), bin2gray_inst return bin2gray_v_inst, stimulus(), bin2gray_inst