additional shadow signal test example

myhdl/_ShadowSignal.py

@@ -94,6 +94,10 @@ class _SliceSignal(_ShadowSignal):
     def _markRead(self):
         self._read = True
         self._sig._read = True
+
+    def _markUsed(self):
+        self._used = True
+        self._sig._read = True
         
 
 #     def toVerilog(self):
@@ -150,6 +154,11 @@ class ConcatSignal(_ShadowSignal):
         for s in self._args:
             s._markRead() 
 
+    def _markUsed(self):
+        self._used = True
+        for s in self._args:
+            s._markUsed() 
+
     def toVHDL(self):
         lines = []
         hi = self._nrbits

myhdl/_Signal.py

@@ -240,6 +240,10 @@ class _Signal(object):
     def _markRead(self):
         self._read = True
 
+    # 'used' attribute
+    def _markUsed(self):
+        self._used = True
+
     # set next methods
     def _setNextBool(self, val):
         if not val in (0, 1):

myhdl/_extractHierarchy.py

@@ -227,7 +227,7 @@ class _HierExtr(object):
                             if isinstance(v, _Signal):
                                 sigdict[n] = v
                                 if n in cellvars:
-                                    v._used = True
+                                    v._markUsed()
                             if _isListOfSigs(v):
                                 m = _makeMemInfo(v)
                                 memdict[n] = m

myhdl/test/conversion/general/test_adapter.py

@@ -0,0 +1,60 @@
+from myhdl import *
+
+def adapter(o_err, i_err, o_spec, i_spec):
+
+    nomatch = Signal(bool(0))
+    other = Signal(bool(0))
+
+    o_err_bits = []
+    for s in o_spec:
+        if s == 'other':
+            o_err_bits.append(other)
+        elif s == 'nomatch':
+            o_err_bits.append(nomatch)
+        else:
+            bit = i_err(i_spec[s])
+            o_err_bits.append(bit)
+    o_err_vec = ConcatSignal(*o_err_bits)
+
+    other_bits = []
+    for s, i in i_spec.items():
+        if s in o_spec:
+            continue
+        bit = i_err(i)
+        other_bits.append(bit)
+    other_vec = ConcatSignal(*other_bits)
+
+    @always_comb
+    def assign():
+ 	nomatch.next = 0
+        other.next = (other_vec != 0)
+        o_err.next = o_err_vec
+
+    return assign
+
+
+
+def bench_adapter():
+    o_spec = ('c', 'a', 'other', 'nomatch')
+    i_spec = { 'a' : 1, 'b' : 2, 'c' : 0, 'd' : 3, 'e' : 4, 'f' : 5, }
+
+    o_err = Signal(intbv(0)[4:])
+    i_err = Signal(intbv(0)[6:])
+    
+    dut = adapter(o_err, i_err, o_spec, i_spec)
+
+    @instance
+    def stimulus():
+        for i in range(2**len(i_err)):
+            i_err.next = i
+            yield delay(10)
+            assert o_err[0] == 0
+            assert o_err[1] == (i_err[2] | i_err[3] | i_err[4] | i_err[5])
+            assert o_err[2] == i_err[1]
+            assert o_err[3] == i_err[0]
+            print o_err
+
+    return dut, stimulus
+
+def test_adapter():
+    assert conversion.verify(bench_adapter) == 0

myhdl/test/core/test_Signal.py

@@ -57,14 +57,6 @@ class SigTest(TestCase):
         self.posedgeWaiters = [object() for i in range(5)]
         self.negedgeWaiters = [object() for i in range(7)]
 
-    def testPublicInterface(self):
-        """ public interface of a sig: val, next, posedge, negedge, min, max, driven, read"""
-        s1 = Signal(1)
-        expected = ['next', 'val', 'posedge', 'negedge', 'min', 'max', 'driven', 'read']
-        iface = [attr for attr in dir(s1) if attr[0] != '_']
-        expected.sort()
-        iface.sort()
-        self.assertEqual(iface, expected)
         
     def testValAttrReadOnly(self):
         """ val attribute should not be writable"""