handle initial reg assignments properly

rewrite always_comb sigdict inference based on function arg only

myhdl/_always_comb.py

@@ -31,7 +31,7 @@ from sets import Set
 
 from myhdl import Signal, AlwaysCombError
 from myhdl._util import _isGenFunc
-
+from myhdl._cell_deref import _cell_deref
 
 class _error:
     pass
@@ -53,12 +53,22 @@ def always_comb(func):
         raise AlwaysCombError(_error.Scope)
     varnames = func.func_code.co_varnames
     sigdict = {}
-    for dict in (f.f_locals, f.f_globals):
-        for n, v in dict.items():
-            if isinstance(v, Signal) and \
-                   n not in varnames and \
-                   n not in sigdict:
-                sigdict[n] = v
+##     for dict in (f.f_locals, f.f_globals):
+##         for n, v in dict.items():
+##             if isinstance(v, Signal) and \
+##                    n not in varnames and \
+##                    n not in sigdict:
+##                 sigdict[n] = v
+    for n, v in func.func_globals.items():
+        if isinstance(v, Signal) and \
+           n not in varnames:
+            sigdict[n] = v
+    # handle free variables
+    if func.func_code.co_freevars:
+        for n, c in zip(func.func_code.co_freevars, func.func_closure):
+            obj = _cell_deref(c)
+            if isinstance(obj, Signal):
+                sigdict[n] = obj
     c = _AlwaysComb(func, sigdict)
     return c
    

myhdl/_toVerilog/_convert.py

@@ -136,9 +136,9 @@ def _writeSigDecls(f, intf, siglist):
             continue
         r = _getRangeString(s)
         if s._driven:
-            # the following line would implement  initial value assignments
-            # print >> f, "reg %s%s = %s;" % (r, s._name, int(s._val))
-            print >> f, "reg %s%s;" % (r, s._name)
+            # the following line implements initial value assignments
+            print >> f, "reg %s%s = %s;" % (r, s._name, int(s._val))
+            # print >> f, "reg %s%s;" % (r, s._name)
         elif s._read:
             # the original exception
             # raise ToVerilogError(_error.UndrivenSignal, s._name)
@@ -237,16 +237,26 @@ class _ConvertVisitor(_ToVerilogMixin):
     def writeDeclaration(self, obj, name, dir):
         if dir: dir = dir + ' '
         if type(obj) is bool:
-            self.write("%s%s;" % (dir, name))
+            self.write("%s%s" % (dir, name))
         elif isinstance(obj, int):
             if dir == "input ":
                 self.write("input %s;" % name)
                 self.writeline()
-            self.write("integer %s;" % name)
+            self.write("integer %s" % name)
         elif hasattr(obj, '_nrbits'):
-            self.write("%s[%s-1:0] %s;" % (dir, obj._nrbits, name))
+            self.write("%s[%s-1:0] %s" % (dir, obj._nrbits, name))
         else:
             raise AssertionError("var %s has unexpected type %s" % (name, type(obj)))
+        # initialize regs
+        if dir == 'reg ':
+            if str(type(obj)) == "<class 'myhdl._enum.EnumItem'>":
+                inival = obj._toVerilog()
+            else:
+                inival = int(obj)
+            self.write(" = %s;" % inival)
+        else:
+            self.write(";")
+        
 
     def writeDeclarations(self):
         for name, obj in self.ast.vardict.items():

myhdl/test/test_always_comb.py

@@ -110,7 +110,6 @@ class AlwaysCombCompilationTest(TestCase):
 
     def testInfer3(self):
         a, b, c, d = [Signal(0) for i in range(4)]
-        d = Signal(0)
         u = 1
         def h():
             c.next = a + x + u

myhdl/test/toVerilog/test_misc.py

@@ -117,6 +117,15 @@ def adderTranslateOn(a, b, c):
             import string
         c.next = a + b
 
+def adderLocal(a, b, c):
+    debug = False
+    while 1:
+        yield a, b
+        if debug:
+            c.next = a + b
+        debug = not debug
+        
+
         
 def Ignorecode_v(a, b, c):
     objfile = "ignorecode.o"           
@@ -137,6 +146,7 @@ class TestIgnoreCode(unittest.TestCase):
         c_v = Signal(intbv(0)[9:])
 
         ignorecode_inst = toVerilog(adder, a, b, c)
+        # ignorecode_inst = adder(a, b, c)
         ignorecode_v_inst = Ignorecode_v(a, b, c_v)
 
         def stimulus():
@@ -160,6 +170,10 @@ class TestIgnoreCode(unittest.TestCase):
         sim = self.bench(adderTranslateOn)
         Simulation(sim).run()
 
+    def testAdderLocal(self):
+        sim = self.bench(adderLocal)
+        Simulation(sim).run()
+
         
 if __name__ == '__main__':
     unittest.main()