lot of progrees on tracing

myhdl/Signal.py

@@ -33,7 +33,7 @@ __date__ = "$Date$"
 from __future__ import generators
 from copy import deepcopy as copy
 
-import _simulator
+import _simulator as sim
 from _simulator import _siglist, _futureEvents, now
 from myhdl import intbv
 from bin import bin
@@ -65,9 +65,10 @@ class Signal(object):
 
     """
 
-    __slots__ = ('_next', '_val', '_type',
+    __slots__ = ('_next', '_val', '_min', '_max', '_type', 
                  '_eventWaiters', '_posedgeWaiters', '_negedgeWaiters',
-                 '_codeName', '_tracing', 
+                 '_code', '_tracing', '_nrbits', '_hasBounds',
+                 '_printVcd'
                 )
 
     def __new__(cls, val, delay=0):
@@ -84,14 +85,35 @@ class Signal(object):
         
         """
         self._next = self._val = val
-        if type(val) in (int, long, intbv):
+        self._min = self._max = self._nrbits = None
-            self._type = (int, long, intbv)
+        self._type = (int, long, intbv)
+        self._printVcd = self._printVcdStr
+        if type(val) is bool:
+            self._min = 0
+            self._max = 1
+            self._nrbits = 1
+        elif isinstance(val, (int, long)):
+            self._printVcd = self._printVcdHex
+        elif isinstance(val, intbv):
+            self._printVcd = self._printVcdHex
+            self._min = val._min
+            self._max = val._max
+            if val._len:
+                self._nrbits = val._len
+            elif val._min is not None and val._max is not None:
+                self._nrbits = max(len(bin(val._min)), len(bin(val._max-1)))
         else:
             self._type = type(val)
+        if self._nrbits:
+            if self._nrbits == 1:
+                self._printVcd = self._printVcdBit
+            else:
+                self._printVcd = self._printVcdVec
+        self._hasBounds = (self._min is not None) or (self._max is not None)
         self._eventWaiters = _WaiterList()
         self._posedgeWaiters = _WaiterList()
         self._negedgeWaiters = _WaiterList()
-        self._codeName = ""
+        self._code = ""
         self._tracing = 0
         
     def _update(self):
@@ -106,7 +128,7 @@ class Signal(object):
                 del self._negedgeWaiters[:]
             self._val = self._next
             if self._tracing:
-                print >> _simulator._tracefile, "b%s %s" % (bin(self._val, 8), self._codeName)
+                self._printVcd()
             return waiters
         else:
             return []
@@ -142,7 +164,18 @@ class Signal(object):
     def _get_negedge(self):
         return self._negedgeWaiters
     negedge = property(_get_negedge, None, None, "'posedge' access methodes")
-    
+
+    def _printVcdStr(self):
+        print >> sim._tf, "s%s %s" % (str(self._val), self._code)
+        
+    def _printVcdHex(self):
+        print >> sim._tf, "s%s %s" % (hex(self._val), self._code)
+
+    def _printVcdBit(self):
+        print >> sim._tf, "%d%s" % (self._val, self._code)
+
+    def _printVcdVec(self):
+        print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code)
 
     # hashing not supported
     def __hash__(self):
@@ -331,9 +364,9 @@ class DelayedSignal(Signal):
 
     def _update(self):
         if self._next != self._nextZ:
-            self._timeStamp = _simulator._time
+            self._timeStamp = sim._time
         self._nextZ = self._next
-        t = _simulator._time + self._delay
+        t = sim._time + self._delay
         _schedule((t, _SignalWrap(self, self._next, self._timeStamp)))
         return []
 

myhdl/Simulation.py

@@ -116,7 +116,7 @@ class Simulation(object):
         t = _simulator._time
         actives = {}
         tracing = _simulator._tracing
-        tracefile = _simulator._tracefile
+        tracefile = _simulator._tf
 
         while 1:
             try:

myhdl/_simulator.py

@@ -33,7 +33,7 @@ _futureEvents = []
 _time = 0
 _cosim = 0
 _tracing = 0
-_tracefile = None
+_tf = None
 
 def now():
     """ Return the current simulation time """

myhdl/test_Signal.py

@@ -29,6 +29,7 @@ from random import randrange
 random.seed(1) # random, but deterministic
 import sys
 maxint = sys.maxint
+import types
 
 import unittest
 from unittest import TestCase
@@ -536,9 +537,37 @@ class TestSignalIntBvIndexing(TestCase):
             pass
         else:
             self.fail()
+
+
+class TestSignalNrBits(TestCase):
+
+    def testBool(self):
+        if type(bool) is not types.TypeType: # bool not a type in 2.2
+            return
+        s = Signal(bool())
+        self.assertEqual(s._nrbits, 1)
+
+    def testIntbvSlice(self):
+        for n in range(1, 40):
+            for m in range(0, n):
+                s = Signal(intbv()[n:m])
+                self.assertEqual(s._nrbits, n-m)
+
+    def testIntbvBounds(self):
+        for n in range(1, 40):
+            s = Signal(intbv(min=0, max=2**n))
+            self.assertEqual(s._nrbits, n)
+            s = Signal(intbv(1, min=1, max=2**n))
+            self.assertEqual(s._nrbits, n)
+            s = Signal(intbv(min=0, max=2**n+1))
+            self.assertEqual(s._nrbits, n+1)
+            s = Signal(intbv(min=-(2**n), max=2**n-1))
+            self.assertEqual(s._nrbits, n+1)
+            s = Signal(intbv(min=-(2**n), max=1))
+            self.assertEqual(s._nrbits, n+1)
+            s = Signal(intbv(min=-(2**n)-1, max=2**n-1))
+            self.assertEqual(s._nrbits, n+2)
             
-            
-              
 
 if __name__ == "__main__":
     unittest.main()

myhdl/trace_sigs.py

@@ -61,11 +61,11 @@ def trace_sigs(dut, *args, **kwargs):
     h = HierExtr(name, dut, *args, **kwargs)
     vcdfilename = name + ".vcd"
     vcdfile = open(vcdfilename, 'w')
+    _simulator._tracing = 1
+    _simulator._tf = vcdfile
     _writeVcdHeader(vcdfile)
     _writeVcdSigs(vcdfile, h.instances)
     _tracing = 0
-    _simulator._tracing = 1
-    _simulator._tracefile = vcdfile
     return h.m
  
 
@@ -82,7 +82,7 @@ class HierExtr(object):
             sys.setprofile(None)
         self.m = _top
         instances.reverse()
-        print instances
+        # print instances
         instances[0][1] = name
 
     def extractor(self, frame, event, arg):
@@ -144,6 +144,7 @@ def _writeVcdHeader(f):
 def _writeVcdSigs(f, instances):
     curlevel = 0
     namegen = _genNameCode()
+    siglist = []
     for level, name, sigdict in instances:
         delta = curlevel - level
         curlevel = level
@@ -155,13 +156,24 @@ def _writeVcdSigs(f, instances):
         for n, s in sigdict.items():
             if not s._tracing:
                 s._tracing = 1
-                s._codeName = namegen.next()
+                s._code = namegen.next()
-            print >> f, "$var reg 8 %s %s $end" % (s._codeName, n)
+                siglist.append(s)
+            w = s._nrbits
+            if w:
+                if w == 1:
+                    print >> f, "$var reg 1 %s %s $end" % (s._code, n)
+                else:
+                    print >> f, "$var reg %s %s %s $end" % (w, s.code, n)
+            else:
+                print >> f, "$var real 1 %s %s $end" % (s._code, n)
     for i in range(curlevel):
         print >> f, "$upscope $end"
     print >> f
     print >> f, "$enddefinitions $end"
     print >> f, "$dumpvars"
+    for s in siglist:
+        s._printVcd() # initial value
+    print >> f, "$end"