mirror of
https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
Initial MEP:107 support.
All arguments in the top level must be signals, apart from that, you can access attributes in generators. --HG-- branch : mep107
This commit is contained in:
Keerthan Jaic
parent
247d0379e2
commit
e0b6219bed
@ -31,6 +31,7 @@ from myhdl._util import _isGenFunc, _dedent
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from myhdl._cell_deref import _cell_deref
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from myhdl._Waiter import _Waiter, _SignalWaiter, _SignalTupleWaiter
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from myhdl._instance import _Instantiator
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from myhdl._resolverefs import _AttrRefTransformer
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class _error:
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pass
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@ -40,7 +41,7 @@ _error.Scope = "always_comb argument should be a local function"
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_error.SignalAsInout = "signal (%s) used as inout in always_comb function argument"
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_error.EmbeddedFunction = "embedded functions in always_comb function argument not supported"
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_error.EmptySensitivityList= "sensitivity list is empty"
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def always_comb(func):
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if not isinstance( func, FunctionType):
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raise AlwaysCombError(_error.ArgType)
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@ -63,7 +64,7 @@ def always_comb(func):
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raise NameError(n)
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c = _AlwaysComb(func, symdict)
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return c
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INPUT, OUTPUT, INOUT = range(3)
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@ -115,7 +116,7 @@ class _SigNameVisitor(ast.NodeVisitor):
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raise AlwaysCombError(_error.SignalAsInout % id)
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else:
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raise AssertionError("bug in always_comb")
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def visit_Assign(self, node):
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self.context = OUTPUT
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for n in node.targets:
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@ -136,7 +137,7 @@ class _SigNameVisitor(ast.NodeVisitor):
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self.visit(node.target)
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self.context = INPUT
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self.visit(node.value)
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def visit_ClassDef(self, node):
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pass # skip
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@ -146,7 +147,7 @@ class _SigNameVisitor(ast.NodeVisitor):
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def visit_Print(self, node):
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pass # skip
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class _AlwaysComb(_Instantiator):
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@ -186,7 +187,9 @@ class _AlwaysComb(_Instantiator):
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s = _dedent(s)
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tree = ast.parse(s)
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# print ast.dump(tree)
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v = _SigNameVisitor(symdict)
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v = _AttrRefTransformer(self)
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v.visit(tree)
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v = _SigNameVisitor(self.symdict)
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v.visit(tree)
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self.inputs = v.inputs
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self.outputs = v.outputs
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@ -217,7 +220,7 @@ class _AlwaysComb(_Instantiator):
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while 1:
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func()
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yield senslist
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@ -34,10 +34,11 @@ from myhdl import ExtractHierarchyError, ToVerilogError, ToVHDLError
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from myhdl._Signal import _Signal, _isListOfSigs
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from myhdl._util import _isGenFunc
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from myhdl._misc import _isGenSeq
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from myhdl._resolverefs import _resolveRefs
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_profileFunc = None
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class _error:
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pass
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_error.NoInstances = "No instances found"
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@ -46,8 +47,8 @@ _error.InconsistentToplevel = "Inconsistent top level %s for %s - should be 1"
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class _Instance(object):
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__slots__ = ['level', 'obj', 'subs', 'sigdict', 'memdict', 'name', 'func', 'argdict']
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def __init__(self, level, obj, subs, sigdict, memdict, func, argdict):
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__slots__ = ['level', 'obj', 'subs', 'sigdict', 'memdict', 'name', 'func', 'argdict', 'objdict']
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def __init__(self, level, obj, subs, sigdict, memdict, func, argdict, objdict=None):
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self.level = level
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self.obj = obj
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self.subs = subs
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@ -55,7 +56,9 @@ class _Instance(object):
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self.memdict = memdict
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self.func = func
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self.argdict = argdict
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if objdict:
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self.objdict = objdict
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_memInfoMap = {}
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@ -79,7 +82,7 @@ def _makeMemInfo(mem):
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if key not in _memInfoMap:
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_memInfoMap[key] = _MemInfo(mem)
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return _memInfoMap[key]
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def _isMem(mem):
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return id(mem) in _memInfoMap
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@ -108,10 +111,10 @@ class _UserCode(object):
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self.raiseError(msg, info)
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code = "\n%s\n" % code
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return code
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def _interpolate(self):
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return string.Template(self.code).substitute(self.namespace)
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class _UserCodeDepr(_UserCode):
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def _interpolate(self):
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return self.code % self.namespace
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@ -119,18 +122,18 @@ class _UserCodeDepr(_UserCode):
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class _UserVerilogCode(_UserCode):
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def raiseError(self, msg, info):
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raise ToVerilogError("Error in user defined Verilog code", msg, info)
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class _UserVhdlCode(_UserCode):
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def raiseError(self, msg, info):
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raise ToVHDLError("Error in user defined VHDL code", msg, info)
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class _UserVerilogCodeDepr(_UserVerilogCode, _UserCodeDepr):
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pass
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class _UserVhdlCodeDepr(_UserVhdlCode, _UserCodeDepr):
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pass
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class _UserVerilogInstance(_UserVerilogCode):
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def __str__(self):
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args = inspect.getargspec(self.func)[0]
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@ -159,8 +162,8 @@ class _UserVhdlInstance(_UserVhdlCode):
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s += "\n %s=>%s" % (arg, signame)
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s += "\n );\n\n"
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return s
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def _addUserCode(specs, arg, funcname, func, frame):
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classMap = {
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@ -170,7 +173,7 @@ def _addUserCode(specs, arg, funcname, func, frame):
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'vhdl_code' :_UserVhdlCode,
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'verilog_instance' : _UserVerilogInstance,
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'vhdl_instance' :_UserVhdlInstance,
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}
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namespace = frame.f_globals.copy()
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namespace.update(frame.f_locals)
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@ -192,13 +195,13 @@ def _addUserCode(specs, arg, funcname, func, frame):
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assert id(arg) not in _userCodeMap[hdl]
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code = specs[spec]
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_userCodeMap[hdl][id(arg)] = classMap[spec](code, namespace, funcname, func, sourcefile, sourceline)
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class _CallFuncVisitor(object):
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def __init__(self):
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self.linemap = {}
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def visitAssign(self, node):
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if isinstance(node.expr, ast.CallFunc):
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self.lineno = None
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@ -207,13 +210,13 @@ class _CallFuncVisitor(object):
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def visitName(self, node):
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self.lineno = node.lineno
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class _HierExtr(object):
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def __init__(self, name, dut, *args, **kwargs):
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global _profileFunc
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_memInfoMap.clear()
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for hdl in _userCodeMap:
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@ -262,28 +265,28 @@ class _HierExtr(object):
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names[id(soi)] = sni
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absnames[id(soi)] = "%s_%s_%s" % (tn, sn, i)
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def extractor(self, frame, event, arg):
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if event == "call":
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funcname = frame.f_code.co_name
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# skip certain functions
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if funcname in self.skipNames:
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self.skip +=1
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if not self.skip:
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self.level += 1
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elif event == "return":
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funcname = frame.f_code.co_name
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func = frame.f_globals.get(funcname)
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func = frame.f_globals.get(funcname)
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if func is None:
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# Didn't find a func in the global space, try the local "self"
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# argument and see if it has a method called *funcname*
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obj = frame.f_locals.get('self')
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if hasattr(obj, funcname):
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func = getattr(obj, funcname)
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func = getattr(obj, funcname)
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if not self.skip:
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isGenSeq = _isGenSeq(arg)
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if isGenSeq:
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@ -298,65 +301,75 @@ class _HierExtr(object):
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spec = "%s_instance" % hdl
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if func and hasattr(func, spec) and getattr(func, spec):
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specs[spec] = getattr(func, spec)
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if specs:
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if specs:
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_addUserCode(specs, arg, funcname, func, frame)
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# building hierarchy only makes sense if there are generators
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if isGenSeq and arg:
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sigdict = {}
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memdict = {}
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argdict = {}
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argdict = {}
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if func:
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arglist = inspect.getargspec(func).args
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arglist = inspect.getargspec(func).args
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else:
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arglist = []
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cellvars = frame.f_code.co_cellvars
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for dict in (frame.f_globals, frame.f_locals):
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for n, v in dict.items():
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# extract signals and memories
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# also keep track of whether they are used in generators
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# only include objects that are used in generators
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symdict = frame.f_globals.copy()
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symdict.update(frame.f_locals)
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cellvars = []
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cellvars.extend(frame.f_code.co_cellvars)
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if self.level > 1:
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objlist = _resolveRefs(symdict, arg)
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cellvars.extend(objlist)
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#for dict in (frame.f_globals, frame.f_locals):
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for n, v in symdict.items():
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# extract signals and memories
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# also keep track of whether they are used in generators
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# only include objects that are used in generators
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## if not n in cellvars:
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## continue
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if isinstance(v, _Signal):
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sigdict[n] = v
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if n in cellvars:
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v._markUsed()
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if _isListOfSigs(v):
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m = _makeMemInfo(v)
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memdict[n] = m
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if n in cellvars:
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m._used = True
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# save any other variable in argdict
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if (n in arglist) and (n not in sigdict) and (n not in memdict):
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argdict[n] = v
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if isinstance(v, _Signal):
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sigdict[n] = v
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if n in cellvars:
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v._markUsed()
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if _isListOfSigs(v):
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m = _makeMemInfo(v)
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memdict[n] = m
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if n in cellvars:
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m._used = True
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# save any other variable in argdict
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if (n in arglist) and (n not in sigdict) and (n not in memdict):
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argdict[n] = v
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subs = []
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for n, sub in frame.f_locals.items():
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for elt in _inferArgs(arg):
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if elt is sub:
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subs.append((n, sub))
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inst = _Instance(self.level, arg, subs, sigdict, memdict, func, argdict)
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self.hierarchy.append(inst)
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self.level -= 1
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if funcname in self.skipNames:
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self.skip -= 1
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def _inferArgs(arg):
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c = [arg]
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if isinstance(arg, (tuple, list)):
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c += list(arg)
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return c
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@ -42,6 +42,7 @@ from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode
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from myhdl._Signal import _Signal, _WaiterList
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from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal
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from myhdl._util import _isTupleOfInts, _dedent
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from myhdl._resolverefs import _AttrRefTransformer
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myhdlObjects = myhdl.__dict__.values()
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builtinObjects = __builtin__.__dict__.values()
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@ -72,7 +73,7 @@ def _makeAST(f):
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tree.sourcefile = inspect.getsourcefile(f)
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tree.lineoffset = inspect.getsourcelines(f)[1]-1
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return tree
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def _analyzeSigs(hierarchy, hdl='Verilog'):
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curlevel = 0
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siglist = []
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@ -81,7 +82,7 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
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open, close = '[', ']'
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if hdl == 'VHDL':
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open, close = '(', ')'
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for inst in hierarchy:
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level = inst.level
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name = inst.name
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@ -91,8 +92,8 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
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curlevel = level
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assert(delta >= -1)
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if delta > -1: # same or higher level
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prefixes = prefixes[:curlevel-1]
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# skip processing and prefixing in context without signals
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prefixes = prefixes[:curlevel-1]
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# skip processing and prefixing in context without signals
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if not (sigdict or memdict):
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prefixes.append("")
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continue
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@ -100,6 +101,10 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
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for n, s in sigdict.items():
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if s._name is not None:
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continue
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if '.' in n:
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n = n.replace('.', '_')
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while n in sigdict:
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n = n + '_'
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if isinstance(s, _SliceSignal):
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continue
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s._name = _makeName(n, prefixes)
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@ -133,10 +138,10 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
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raise ConversionError(_error.InconsistentType, s._name)
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if s._nrbits != m.elObj._nrbits:
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raise ConversionError(_error.InconsistentBitWidth, s._name)
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return siglist, memlist
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def _analyzeGens(top, absnames):
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genlist = []
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@ -158,21 +163,24 @@ def _analyzeGens(top, absnames):
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if f.func_code.co_freevars:
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for n, c in zip(f.func_code.co_freevars, f.func_closure):
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obj = _cell_deref(c)
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if isinstance(g, _AlwaysComb):
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if not ( isinstance(obj, (int, long, EnumType,_Signal)) or \
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_isMem(obj) or _isTupleOfInts(obj)
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):
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info = "File %s, line %s: " % (tree.sourcefile, tree.lineoffset)
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print type(obj)
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raise ConversionError(_error.UnsupportedType, n, info)
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tree.symdict[n] = obj
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# currently, only intbv as automatic nonlocals (until Python 3.0)
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if isinstance(obj, intbv):
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tree.nonlocaldict[n] = obj
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tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()
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v = _AttrRefTransformer(tree)
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v.visit(tree)
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v = _FirstPassVisitor(tree)
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v.visit(tree)
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if isinstance(g, _AlwaysComb):
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objs = [tree.symdict[objname] for objname in tree.objlist]
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for obj in objs:
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if not ( isinstance(obj, (int, long, EnumType,_Signal)) or \
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_isMem(obj) or _isTupleOfInts(obj)
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):
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info = "File %s, line %s: " % (tree.sourcefile, tree.lineoffset)
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print type(obj)
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raise ConversionError(_error.UnsupportedType, n, info)
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v = _AnalyzeAlwaysCombVisitor(tree, g.senslist)
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elif isinstance(g, _AlwaysSeq):
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v = _AnalyzeAlwaysSeqVisitor(tree, g.senslist, g.reset, g.sigregs, g.varregs)
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@ -192,6 +200,8 @@ def _analyzeGens(top, absnames):
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tree.nonlocaldict = {}
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tree.callstack = []
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tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()
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v = _AttrRefTransformer(tree)
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v.visit(tree)
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v = _FirstPassVisitor(tree)
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v.visit(tree)
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v = _AnalyzeBlockVisitor(tree)
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@ -203,15 +213,15 @@ def _analyzeGens(top, absnames):
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class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
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"""First pass visitor.
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Prune unsupported contructs, and add some useful attributes.
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"""
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def __init__(self, tree):
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self.tree = tree
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self.toplevel = True
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def visit_Tuple(self, node):
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if isinstance(node.ctx, ast.Store):
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self.raiseError(node, _error.NotSupported, "tuple assignment")
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@ -266,13 +276,13 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
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def visit_TryFinally(self, node):
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self.raiseError(node, _error.NotSupported, "try-finally statement")
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def visit_Assign(self, node):
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if len(node.targets) > 1:
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self.raiseError(node, _error.NotSupported, "multiple assignments")
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self.visit(node.targets[0])
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self.visit(node.value)
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def visit_Call(self, node):
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if node.starargs:
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self.raiseError(node, _error.NotSupported, "extra positional arguments")
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@ -280,12 +290,12 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
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||||
self.raiseError(node, _error.NotSupported, "extra named arguments")
|
||||
# f = eval(_unparse(node.node), self.tree.symdict)
|
||||
self.generic_visit(node)
|
||||
|
||||
|
||||
def visit_Compare(self, node):
|
||||
if len(node.ops) != 1:
|
||||
self.raiseError(node, _error.NotSupported, "chained comparison")
|
||||
self.generic_visit(node)
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
if node.args.vararg or node.args.kwarg:
|
||||
self.raiseError(node, _error.NotSupported, "extra positional or named arguments")
|
||||
@ -301,7 +311,7 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
node.doc = node.body[0].value.s
|
||||
node.body = node.body[1:]
|
||||
self.visitList(node.body)
|
||||
|
||||
|
||||
def flattenIf(self, node, tests, else_, co):
|
||||
""" Flatten if-then-else as in compiler package."""
|
||||
if node:
|
||||
@ -323,7 +333,7 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
node.ignore = True
|
||||
return # skip
|
||||
self.generic_visit(node)
|
||||
|
||||
|
||||
# add fields that match old compiler package
|
||||
tests = [(node.test, node.body)]
|
||||
else_ = []
|
||||
@ -337,7 +347,7 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.raiseError(node, _error.NotSupported, "printing to a file with >> syntax")
|
||||
if not node.nl:
|
||||
self.raiseError(node, _error.NotSupported, "printing without newline")
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -405,10 +415,10 @@ def _getNritems(obj):
|
||||
return len(obj._type)
|
||||
else:
|
||||
raise TypeError("Unexpected type")
|
||||
|
||||
|
||||
|
||||
class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
|
||||
def __init__(self, tree):
|
||||
tree.sigdict = {}
|
||||
tree.vardict = {}
|
||||
@ -441,7 +451,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
if not hasType(n.obj, bool):
|
||||
self.raiseError(node, _error.NotSupported, "non-boolean argument in logical operator")
|
||||
node.obj = bool()
|
||||
|
||||
|
||||
def visit_UnaryOp(self, node):
|
||||
self.visit(node.operand)
|
||||
op = node.op
|
||||
@ -465,7 +475,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
if isinstance(obj, _Signal) and isinstance(obj._init, modbv):
|
||||
if not obj._init._hasFullRange():
|
||||
self.raiseError(node, _error.ModbvRange, n)
|
||||
|
||||
|
||||
def setAttr(self, node):
|
||||
if node.attr != 'next':
|
||||
self.raiseError(node, _error.NotSupported, "attribute assignment")
|
||||
@ -505,7 +515,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
obj._setName(n+suf)
|
||||
if node.obj is None: # attribute lookup failed
|
||||
self.raiseError(node, _error.UnsupportedAttribute, node.attr)
|
||||
|
||||
|
||||
def visit_Assign(self, node):
|
||||
target, value = node.targets[0], node.value
|
||||
self.access = _access.OUTPUT
|
||||
@ -557,7 +567,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
def visit_Break(self, node):
|
||||
self.labelStack[-2].isActive = True
|
||||
|
||||
|
||||
def visit_Call(self, node):
|
||||
self.visit(node.func)
|
||||
self.access = _access.UNKNOWN
|
||||
@ -655,7 +665,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
if isinstance(val, bool):
|
||||
val = int(val) # cast bool to int first
|
||||
if isinstance(val, (EnumItemType, int, long)):
|
||||
node.case = (node.left, val)
|
||||
node.case = (node.left, val)
|
||||
# check whether it can be part of an edge check
|
||||
n = node.left.id
|
||||
if n in self.tree.sigdict:
|
||||
@ -680,7 +690,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
def visit_Str(self, node):
|
||||
node.obj = node.s
|
||||
|
||||
|
||||
def visit_Continue(self, node):
|
||||
self.labelStack[-1].isActive = True
|
||||
|
||||
@ -693,20 +703,20 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.visit(node.target)
|
||||
var = node.target.id
|
||||
self.tree.vardict[var] = int(-1)
|
||||
|
||||
|
||||
cf = node.iter
|
||||
self.visit(cf)
|
||||
self.require(node, isinstance(cf, ast.Call), "Expected (down)range call")
|
||||
f = self.getObj(cf.func)
|
||||
self.require(node, f in (range, downrange), "Expected (down)range call")
|
||||
|
||||
|
||||
for stmt in node.body:
|
||||
self.visit(stmt)
|
||||
self.refStack.pop()
|
||||
self.require(node, not node.orelse, "for-else not supported")
|
||||
self.labelStack.pop()
|
||||
self.labelStack.pop()
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
raise AssertionError("subclass must implement this")
|
||||
|
||||
@ -816,7 +826,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
sig._driven = 'wire'
|
||||
if not isinstance(sig, _Signal):
|
||||
# print "not a signal: %s" % n
|
||||
pass
|
||||
pass
|
||||
else:
|
||||
if sig._type is bool:
|
||||
node.edge = sig.posedge
|
||||
@ -835,7 +845,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.tree.outputs.add(n)
|
||||
elif self.access == _access.UNKNOWN:
|
||||
pass
|
||||
else:
|
||||
else:
|
||||
self.raiseError(node, _error.NotSupported, "Augmented signal assignment")
|
||||
if n in self.tree.vardict:
|
||||
obj = self.tree.vardict[n]
|
||||
@ -887,7 +897,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
node.obj = __builtin__.__dict__[n]
|
||||
else:
|
||||
self.raiseError(node, _error.UnboundLocal, n)
|
||||
|
||||
|
||||
def visit_Return(self, node):
|
||||
self.raiseError(node, _error.NotSupported, "return statement")
|
||||
|
||||
@ -945,7 +955,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
if len(node.args) > nr:
|
||||
self.raiseError(node, _error.FormatString, "too many arguments")
|
||||
self.generic_visit(node)
|
||||
|
||||
|
||||
def visit_Subscript(self, node):
|
||||
if isinstance(node.slice, ast.Slice):
|
||||
self.accessSlice(node)
|
||||
@ -970,7 +980,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
else:
|
||||
rightind = 0
|
||||
node.obj = node.obj[leftind:rightind]
|
||||
|
||||
|
||||
def accessIndex(self, node):
|
||||
self.visit(node.value)
|
||||
self.access = _access.INPUT
|
||||
@ -1033,15 +1043,15 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.raiseError(node, _error.UnsupportedYield)
|
||||
node.senslist = senslist
|
||||
|
||||
|
||||
|
||||
class _AnalyzeBlockVisitor(_AnalyzeVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree):
|
||||
_AnalyzeVisitor.__init__(self, tree)
|
||||
for n, v in self.tree.symdict.items():
|
||||
if isinstance(v, _Signal):
|
||||
self.tree.sigdict[n] = v
|
||||
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
self.refStack.push()
|
||||
@ -1058,7 +1068,7 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
|
||||
self.tree.kind = _kind.INITIAL
|
||||
self.refStack.pop()
|
||||
|
||||
|
||||
|
||||
def visit_Module(self, node):
|
||||
self.generic_visit(node)
|
||||
for n in self.tree.outputs:
|
||||
@ -1069,8 +1079,8 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
|
||||
for n in self.tree.inputs:
|
||||
s = self.tree.sigdict[n]
|
||||
s._markRead()
|
||||
|
||||
|
||||
|
||||
|
||||
def visit_Return(self, node):
|
||||
### value should be None
|
||||
if node.value is None:
|
||||
@ -1084,7 +1094,7 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
|
||||
|
||||
|
||||
class _AnalyzeAlwaysCombVisitor(_AnalyzeBlockVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, senslist):
|
||||
_AnalyzeBlockVisitor.__init__(self, tree)
|
||||
self.tree.senslist = senslist
|
||||
@ -1124,10 +1134,10 @@ class _AnalyzeAlwaysCombVisitor(_AnalyzeBlockVisitor):
|
||||
for n in self.tree.outmems:
|
||||
m = _getMemInfo(self.tree.symdict[n])
|
||||
m._driven = "wire"
|
||||
|
||||
|
||||
|
||||
|
||||
class _AnalyzeAlwaysSeqVisitor(_AnalyzeBlockVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, senslist, reset, sigregs, varregs):
|
||||
_AnalyzeBlockVisitor.__init__(self, tree)
|
||||
self.tree.senslist = senslist
|
||||
@ -1135,22 +1145,22 @@ class _AnalyzeAlwaysSeqVisitor(_AnalyzeBlockVisitor):
|
||||
self.tree.sigregs = sigregs
|
||||
self.tree.varregs = varregs
|
||||
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
self.refStack.push()
|
||||
for n in node.body:
|
||||
self.visit(n)
|
||||
self.tree.kind = _kind.ALWAYS_SEQ
|
||||
self.refStack.pop()
|
||||
|
||||
|
||||
|
||||
class _AnalyzeAlwaysDecoVisitor(_AnalyzeBlockVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, senslist):
|
||||
_AnalyzeBlockVisitor.__init__(self, tree)
|
||||
self.tree.senslist = senslist
|
||||
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
self.refStack.push()
|
||||
for n in node.body:
|
||||
@ -1158,10 +1168,10 @@ class _AnalyzeAlwaysDecoVisitor(_AnalyzeBlockVisitor):
|
||||
self.tree.kind = _kind.ALWAYS_DECO
|
||||
self.refStack.pop()
|
||||
|
||||
|
||||
|
||||
|
||||
class _AnalyzeFuncVisitor(_AnalyzeVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, args, keywords):
|
||||
_AnalyzeVisitor.__init__(self, tree)
|
||||
self.args = args
|
||||
@ -1169,7 +1179,7 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
|
||||
self.tree.hasReturn = False
|
||||
self.tree.returnObj = None
|
||||
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
self.refStack.push()
|
||||
argnames = [arg.id for arg in node.args.args]
|
||||
@ -1253,7 +1263,7 @@ class _AnalyzeTopFuncVisitor(_AnalyzeVisitor):
|
||||
self.argdict = {}
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
|
||||
|
||||
self.name = node.name
|
||||
argnames = [arg.id for arg in node.args.args]
|
||||
if isboundmethod(self.func):
|
||||
@ -1261,12 +1271,12 @@ class _AnalyzeTopFuncVisitor(_AnalyzeVisitor):
|
||||
self.raiseError(node, _error.NotSupported,
|
||||
"first method argument name other than 'self'")
|
||||
# skip self
|
||||
argnames = argnames[1:]
|
||||
argnames = argnames[1:]
|
||||
i=-1
|
||||
for i, arg in enumerate(self.args):
|
||||
n = argnames[i]
|
||||
if isinstance(arg, _Signal):
|
||||
self.argdict[n] = arg
|
||||
self.argdict[n] = arg
|
||||
if _isMem(arg):
|
||||
self.raiseError(node, _error.ListAsPort, n)
|
||||
for n in argnames[i+1:]:
|
||||
|
||||
@ -60,7 +60,7 @@ def _checkArgs(arglist):
|
||||
for arg in arglist:
|
||||
if not isinstance(arg, (GeneratorType, _Instantiator, _UserVhdlCode)):
|
||||
raise ToVHDLError(_error.ArgType, arg)
|
||||
|
||||
|
||||
def _flatten(*args):
|
||||
arglist = []
|
||||
for arg in args:
|
||||
@ -72,7 +72,7 @@ def _flatten(*args):
|
||||
else:
|
||||
arglist.append(arg)
|
||||
return arglist
|
||||
|
||||
|
||||
def _makeDoc(doc, indent=''):
|
||||
if doc is None:
|
||||
return ''
|
||||
@ -150,11 +150,11 @@ class _ToVHDLConvertor(object):
|
||||
_constDict.clear()
|
||||
_extConstDict.clear()
|
||||
|
||||
siglist, memlist = _analyzeSigs(h.hierarchy, hdl='VHDL')
|
||||
arglist = _flatten(h.top)
|
||||
# print h.top
|
||||
_checkArgs(arglist)
|
||||
genlist = _analyzeGens(arglist, h.absnames)
|
||||
siglist, memlist = _analyzeSigs(h.hierarchy, hdl='VHDL')
|
||||
# print h.top
|
||||
_annotateTypes(genlist)
|
||||
|
||||
### infer interface
|
||||
@ -175,14 +175,14 @@ class _ToVHDLConvertor(object):
|
||||
_enumPortTypeSet.add(obj)
|
||||
|
||||
doc = _makeDoc(inspect.getdoc(func))
|
||||
|
||||
|
||||
needPck = len(_enumPortTypeSet) > 0
|
||||
lib = self.library
|
||||
arch = self.architecture
|
||||
numeric = self.numeric_ports
|
||||
|
||||
|
||||
self._convert_filter(h, intf, siglist, memlist, genlist)
|
||||
|
||||
|
||||
if pfile:
|
||||
_writeFileHeader(pfile, ppath)
|
||||
print >> pfile, _package
|
||||
@ -207,7 +207,7 @@ class _ToVHDLConvertor(object):
|
||||
self._cleanup(siglist)
|
||||
|
||||
return h.top
|
||||
|
||||
|
||||
def _cleanup(self, siglist):
|
||||
# clean up signal names
|
||||
for sig in siglist:
|
||||
@ -215,7 +215,7 @@ class _ToVHDLConvertor(object):
|
||||
# sig._name = None
|
||||
# sig._driven = False
|
||||
# sig._read = False
|
||||
|
||||
|
||||
# clean up attributes
|
||||
self.name = None
|
||||
self.component_declarations = None
|
||||
@ -224,13 +224,13 @@ class _ToVHDLConvertor(object):
|
||||
self.no_myhdl_package = False
|
||||
self.architecture = "MyHDL"
|
||||
self.numeric_ports = True
|
||||
|
||||
|
||||
|
||||
|
||||
def _convert_filter(self, h, intf, siglist, memlist, genlist):
|
||||
# intended to be a entry point for other uses:
|
||||
# intended to be a entry point for other uses:
|
||||
# code checking, optimizations, etc
|
||||
pass
|
||||
|
||||
|
||||
|
||||
toVHDL = _ToVHDLConvertor()
|
||||
|
||||
@ -241,7 +241,7 @@ myhdl_header = """\
|
||||
"""
|
||||
|
||||
def _writeFileHeader(f, fn):
|
||||
vars = dict(filename=fn,
|
||||
vars = dict(filename=fn,
|
||||
version=myhdl.__version__,
|
||||
date=datetime.today().ctime()
|
||||
)
|
||||
@ -404,8 +404,8 @@ def _writeCompDecls(f, compDecls):
|
||||
print >> f, compDecls
|
||||
|
||||
def _writeModuleFooter(f, arch):
|
||||
print >> f, "end architecture %s;" % arch
|
||||
|
||||
print >> f, "end architecture %s;" % arch
|
||||
|
||||
def _getRangeString(s):
|
||||
if isinstance(s._val, EnumItemType):
|
||||
return ''
|
||||
@ -416,7 +416,7 @@ def _getRangeString(s):
|
||||
if ls:
|
||||
msb = ls + '-1'
|
||||
else:
|
||||
msb = s._nrbits-1
|
||||
msb = s._nrbits-1
|
||||
return "(%s downto 0)" % msb
|
||||
else:
|
||||
raise AssertionError
|
||||
@ -513,10 +513,10 @@ opmap = {
|
||||
ast.And : 'and',
|
||||
ast.Or : 'or',
|
||||
}
|
||||
|
||||
|
||||
|
||||
class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
|
||||
def __init__(self, tree, buf):
|
||||
self.tree = tree
|
||||
self.buf = buf
|
||||
@ -526,30 +526,30 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.isLhs = False
|
||||
self.labelStack = []
|
||||
self.context = None
|
||||
|
||||
|
||||
def write(self, arg):
|
||||
self.buf.write("%s" % arg)
|
||||
|
||||
def writeline(self, nr=1):
|
||||
for i in range(nr):
|
||||
self.buf.write("\n%s" % self.ind)
|
||||
|
||||
|
||||
def writeDoc(self, node):
|
||||
assert hasattr(node, 'doc')
|
||||
doc = _makeDoc(node.doc, self.ind)
|
||||
self.write(doc)
|
||||
self.writeline()
|
||||
|
||||
def IntRepr(self, obj):
|
||||
self.writeline()
|
||||
|
||||
def IntRepr(self, obj):
|
||||
if obj >= 0:
|
||||
s = "%s" % int(obj)
|
||||
else:
|
||||
s = "(- %s)" % abs(int(obj))
|
||||
return s
|
||||
|
||||
|
||||
def BitRepr(self, item, var):
|
||||
return '"%s"' % bin(item, len(var))
|
||||
|
||||
|
||||
def inferCast(self, vhd, ori):
|
||||
pre, suf = "", ""
|
||||
if isinstance(vhd, vhd_int):
|
||||
@ -584,13 +584,13 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
pre, suf = "bool(", ")"
|
||||
elif isinstance(vhd, vhd_std_logic):
|
||||
if not isinstance(ori, vhd_std_logic):
|
||||
pre, suf = "stdl(", ")"
|
||||
pre, suf = "stdl(", ")"
|
||||
elif isinstance(vhd, vhd_string):
|
||||
if isinstance(ori, vhd_enum):
|
||||
pre, suf = "%s'image(" % ori._type._name, ")"
|
||||
|
||||
|
||||
return pre, suf
|
||||
|
||||
|
||||
def writeIntSize(self, n):
|
||||
# write size for large integers (beyond 32 bits signed)
|
||||
# with some safety margin
|
||||
@ -615,7 +615,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
if kind: kind += " "
|
||||
if dir: dir += " "
|
||||
self.write("%s%s: %s%s%s" % (kind, name, dir, tipe, endchar))
|
||||
|
||||
|
||||
def writeDeclarations(self):
|
||||
if self.tree.hasPrint:
|
||||
self.writeline()
|
||||
@ -625,7 +625,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
continue # hack for loop vars
|
||||
self.writeline()
|
||||
self.writeDeclaration(obj, name, kind="variable")
|
||||
|
||||
|
||||
def indent(self):
|
||||
self.ind += ' ' * 4
|
||||
|
||||
@ -643,7 +643,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.visit(node.right)
|
||||
else:
|
||||
self.BinOp(node)
|
||||
|
||||
|
||||
def inferBinaryOpCast(self, node, left, right, op):
|
||||
ns, os = node.vhd.size, node.vhdOri.size
|
||||
ds = ns - os
|
||||
@ -671,7 +671,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
if isinstance(op, (ast.Add, ast.Sub, ast.Mod, ast.FloorDiv)):
|
||||
left.vhd.size = ns
|
||||
node.vhdOri.size = ns
|
||||
elif isinstance(op, ast.Mult):
|
||||
elif isinstance(op, ast.Mult):
|
||||
left.vhd.size += ds
|
||||
node.vhdOri.size = 2 * left.vhd.size
|
||||
else:
|
||||
@ -681,14 +681,14 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
right.vhd.size = ns
|
||||
node.vhdOri.size = ns
|
||||
elif isinstance(op, ast.Mult):
|
||||
node.vhdOri.size = 2 * right.vhd.size
|
||||
node.vhdOri.size = 2 * right.vhd.size
|
||||
else:
|
||||
raise AssertionError("unexpected op %s" % op)
|
||||
pre, suf = self.inferCast(node.vhd, node.vhdOri)
|
||||
if pre == "":
|
||||
pre, suf = "(", ")"
|
||||
return pre, suf
|
||||
|
||||
|
||||
def BinOp(self, node):
|
||||
pre, suf = self.inferBinaryOpCast(node, node.left, node.right, node.op)
|
||||
self.write(pre)
|
||||
@ -696,7 +696,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.write(" %s " % opmap[type(node.op)])
|
||||
self.visit(node.right)
|
||||
self.write(suf)
|
||||
|
||||
|
||||
def inferShiftOpCast(self, node, left, right, op):
|
||||
ns, os = node.vhd.size, node.vhdOri.size
|
||||
ds = ns - os
|
||||
@ -706,7 +706,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
node.vhdOri.size = ns
|
||||
pre, suf = self.inferCast(node.vhd, node.vhdOri)
|
||||
return pre, suf
|
||||
|
||||
|
||||
def shiftOp(self, node):
|
||||
pre, suf = self.inferShiftOpCast(node, node.left, node.right, node.op)
|
||||
self.write(pre)
|
||||
@ -716,7 +716,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.visit(node.right)
|
||||
self.write(")")
|
||||
self.write(suf)
|
||||
|
||||
|
||||
def BitOp(self, node):
|
||||
pre, suf = self.inferCast(node.vhd, node.vhdOri)
|
||||
self.write(pre)
|
||||
@ -726,7 +726,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.visit(node.right)
|
||||
self.write(")")
|
||||
self.write(suf)
|
||||
|
||||
|
||||
def visit_BoolOp(self, node):
|
||||
if isinstance(node.vhd, vhd_std_logic):
|
||||
self.write("stdl")
|
||||
@ -736,7 +736,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.write(" %s " % opmap[type(node.op)])
|
||||
self.visit(n)
|
||||
self.write(")")
|
||||
|
||||
|
||||
def visit_UnaryOp(self, node):
|
||||
pre, suf = self.inferCast(node.vhd, node.vhdOri)
|
||||
self.write(pre)
|
||||
@ -745,7 +745,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.visit(node.operand)
|
||||
self.write(")")
|
||||
self.write(suf)
|
||||
|
||||
|
||||
def visit_Attribute(self, node):
|
||||
if isinstance(node.ctx, ast.Store):
|
||||
self.setAttr(node)
|
||||
@ -893,7 +893,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.write(")")
|
||||
self.write(suf)
|
||||
self.write(";")
|
||||
|
||||
|
||||
def visit_Break(self, node):
|
||||
self.write("exit;")
|
||||
|
||||
@ -1012,12 +1012,12 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
# self.write('"%s"' % bin(n, node.vhd.size))
|
||||
elif isinstance(node.vhd, vhd_unsigned):
|
||||
if abs(n) < 2**31:
|
||||
self.write("to_unsigned(%s, %s)" % (n, node.vhd.size))
|
||||
self.write("to_unsigned(%s, %s)" % (n, node.vhd.size))
|
||||
else:
|
||||
self.write('unsigned\'("%s")' % bin(n, node.vhd.size))
|
||||
elif isinstance(node.vhd, vhd_signed):
|
||||
if abs(n) < 2**31:
|
||||
self.write("to_signed(%s, %s)" % (n, node.vhd.size))
|
||||
self.write("to_signed(%s, %s)" % (n, node.vhd.size))
|
||||
else:
|
||||
self.write('signed\'("%s")' % bin(n, node.vhd.size))
|
||||
else:
|
||||
@ -1026,7 +1026,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.write(n)
|
||||
if n < 0:
|
||||
self.write(")")
|
||||
|
||||
|
||||
def visit_Str(self, node):
|
||||
typemark = 'string'
|
||||
if isinstance(node.vhd, vhd_unsigned):
|
||||
@ -1050,7 +1050,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
# ugly hack to detect an orphan "task" call
|
||||
if isinstance(expr, ast.Call) and hasattr(expr, 'tree'):
|
||||
self.write(';')
|
||||
|
||||
|
||||
def visit_IfExp(self, node):
|
||||
pre, suf = self.inferCast(node.vhd, node.body.vhdOri)
|
||||
self.write(pre)
|
||||
@ -1123,7 +1123,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
## self.write("end")
|
||||
self.labelStack.pop()
|
||||
self.labelStack.pop()
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
raise AssertionError("To be implemented in subclass")
|
||||
|
||||
@ -1155,7 +1155,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
if (i == len(node.tests)-1) and not node.else_:
|
||||
self.write("when others")
|
||||
comment = " -- %s" % itemRepr
|
||||
else:
|
||||
else:
|
||||
self.write("when ")
|
||||
self.write(itemRepr)
|
||||
self.write(" =>%s" % comment)
|
||||
@ -1202,13 +1202,13 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.dedent()
|
||||
self.writeline()
|
||||
self.write("end if;")
|
||||
|
||||
|
||||
def visit_ListComp(self, node):
|
||||
pass # do nothing
|
||||
|
||||
def visit_Module(self, node):
|
||||
for stmt in node.body:
|
||||
self.visit(stmt)
|
||||
self.visit(stmt)
|
||||
|
||||
def visit_Name(self, node):
|
||||
if isinstance(node.ctx, ast.Store):
|
||||
@ -1239,7 +1239,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
ori = inferVhdlObj(obj)
|
||||
pre, suf = self.inferCast(node.vhd, ori)
|
||||
s = "%s%s%s" % (pre, s, suf)
|
||||
|
||||
|
||||
elif n in self.tree.argnames:
|
||||
assert n in self.tree.symdict
|
||||
obj = self.tree.symdict[n]
|
||||
@ -1262,9 +1262,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
elif isinstance(node.vhd, vhd_std_logic):
|
||||
s = "stdl(%s)" % n
|
||||
elif isinstance(node.vhd, vhd_unsigned):
|
||||
s = "to_unsigned(%s, %s)" % (n, node.vhd.size)
|
||||
s = "to_unsigned(%s, %s)" % (n, node.vhd.size)
|
||||
elif isinstance(node.vhd, vhd_signed):
|
||||
s = "to_signed(%s, %s)" % (n, node.vhd.size)
|
||||
s = "to_signed(%s, %s)" % (n, node.vhd.size)
|
||||
else:
|
||||
if isinstance(node.vhd, vhd_int):
|
||||
s = self.IntRepr(obj)
|
||||
@ -1272,12 +1272,12 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
s = "'%s'" % int(obj)
|
||||
elif isinstance(node.vhd, vhd_unsigned):
|
||||
if abs(obj) < 2** 31:
|
||||
s = "to_unsigned(%s, %s)" % (n, node.vhd.size)
|
||||
s = "to_unsigned(%s, %s)" % (n, node.vhd.size)
|
||||
else:
|
||||
s = 'unsigned\'("%s")' % bin(obj, node.vhd.size)
|
||||
elif isinstance(node.vhd, vhd_signed):
|
||||
if abs(obj) < 2** 31:
|
||||
s = "to_signed(%s, %s)" % (n, node.vhd.size)
|
||||
s = "to_signed(%s, %s)" % (n, node.vhd.size)
|
||||
else:
|
||||
s = 'signed\'("%s")' % bin(obj, node.vhd.size)
|
||||
elif isinstance(obj, _Signal):
|
||||
@ -1308,7 +1308,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
def visit_Pass(self, node):
|
||||
self.write("null;")
|
||||
|
||||
|
||||
def visit_Print(self, node):
|
||||
argnr = 0
|
||||
for s in node.format:
|
||||
@ -1341,7 +1341,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
def visit_Raise(self, node):
|
||||
self.write('assert False report "End of Simulation" severity Failure;')
|
||||
|
||||
|
||||
def visit_Return(self, node):
|
||||
pass
|
||||
|
||||
@ -1489,9 +1489,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
senslist = [s.sig for s in senslist]
|
||||
return senslist
|
||||
|
||||
|
||||
|
||||
class _ConvertAlwaysVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1538,9 +1538,9 @@ class _ConvertAlwaysVisitor(_ConvertVisitor):
|
||||
self.write("end process %s;" % self.tree.name)
|
||||
self.writeline(2)
|
||||
|
||||
|
||||
|
||||
class _ConvertInitialVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1564,7 +1564,7 @@ class _ConvertInitialVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
class _ConvertAlwaysCombVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1590,9 +1590,9 @@ class _ConvertAlwaysCombVisitor(_ConvertVisitor):
|
||||
self.write("end process %s;" % self.tree.name)
|
||||
self.writeline(2)
|
||||
|
||||
|
||||
|
||||
class _ConvertSimpleAlwaysCombVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1614,7 +1614,7 @@ class _ConvertSimpleAlwaysCombVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
class _ConvertAlwaysDecoVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1653,8 +1653,8 @@ class _ConvertAlwaysDecoVisitor(_ConvertVisitor):
|
||||
self.writeline()
|
||||
self.write("end process %s;" % self.tree.name)
|
||||
self.writeline(2)
|
||||
|
||||
|
||||
|
||||
|
||||
def _convertInitVal(reg, init):
|
||||
pre, suf = '', ''
|
||||
if isinstance(reg, _Signal):
|
||||
@ -1678,10 +1678,10 @@ def _convertInitVal(reg, init):
|
||||
assert isinstance(init, EnumItemType)
|
||||
v = init._toVHDL()
|
||||
return v
|
||||
|
||||
|
||||
|
||||
|
||||
class _ConvertAlwaysSeqVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1743,9 +1743,9 @@ class _ConvertAlwaysSeqVisitor(_ConvertVisitor):
|
||||
self.write("end process %s;" % self.tree.name)
|
||||
self.writeline(2)
|
||||
|
||||
|
||||
|
||||
class _ConvertFunctionVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, funcBuf)
|
||||
self.returnObj = tree.returnObj
|
||||
@ -1762,7 +1762,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
|
||||
obj = self.tree.symdict[name]
|
||||
self.writeline()
|
||||
self.writeDeclaration(obj, name, dir="in", constr=False, endchar="")
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
self.write("function %s(" % self.tree.name)
|
||||
self.indent()
|
||||
@ -1787,9 +1787,9 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
|
||||
self.visit(node.value)
|
||||
self.write(";")
|
||||
|
||||
|
||||
|
||||
class _ConvertTaskVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, funcBuf)
|
||||
self.returnLabel = _Label("RETURN")
|
||||
@ -1806,7 +1806,7 @@ class _ConvertTaskVisitor(_ConvertVisitor):
|
||||
dir = (inout and "inout") or (output and "out") or "in"
|
||||
self.writeline()
|
||||
self.writeDeclaration(obj, name, dir=dir, constr=False, endchar="")
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
self.write("procedure %s" % self.tree.name)
|
||||
if self.tree.argnames:
|
||||
@ -1844,14 +1844,14 @@ class vhd_string(vhd_type):
|
||||
class vhd_enum(vhd_type):
|
||||
def __init__(self, tipe):
|
||||
self._type = tipe
|
||||
|
||||
|
||||
class vhd_std_logic(vhd_type):
|
||||
def __init__(self, size=0):
|
||||
vhd_type.__init__(self)
|
||||
self.size = 1
|
||||
def toStr(self, constr=True):
|
||||
return 'std_logic'
|
||||
|
||||
|
||||
class vhd_boolean(vhd_type):
|
||||
def __init__(self, size=0):
|
||||
vhd_type.__init__(self)
|
||||
@ -1863,7 +1863,7 @@ class vhd_vector(vhd_type):
|
||||
def __init__(self, size=0, lenStr=False):
|
||||
vhd_type.__init__(self, size)
|
||||
self.lenStr = lenStr
|
||||
|
||||
|
||||
class vhd_unsigned(vhd_vector):
|
||||
def toStr(self, constr=True):
|
||||
if constr:
|
||||
@ -1874,7 +1874,7 @@ class vhd_unsigned(vhd_vector):
|
||||
return "unsigned(%s downto 0)" % (self.size-1)
|
||||
else:
|
||||
return "unsigned"
|
||||
|
||||
|
||||
class vhd_signed(vhd_vector):
|
||||
def toStr(self, constr=True):
|
||||
if constr:
|
||||
@ -1885,7 +1885,7 @@ class vhd_signed(vhd_vector):
|
||||
return "signed(%s downto 0)" % (self.size-1)
|
||||
else:
|
||||
return "signed"
|
||||
|
||||
|
||||
class vhd_int(vhd_type):
|
||||
def toStr(self, constr=True):
|
||||
return "integer"
|
||||
@ -1893,7 +1893,7 @@ class vhd_int(vhd_type):
|
||||
class vhd_nat(vhd_int):
|
||||
def toStr(self, constr=True):
|
||||
return "natural"
|
||||
|
||||
|
||||
|
||||
class _loopInt(int):
|
||||
pass
|
||||
@ -1915,7 +1915,7 @@ def maxType(o1, o2):
|
||||
return vhd_int()
|
||||
else:
|
||||
return None
|
||||
|
||||
|
||||
def inferVhdlObj(obj):
|
||||
vhd = None
|
||||
if (isinstance(obj, _Signal) and obj._type is intbv) or \
|
||||
@ -1934,7 +1934,7 @@ def inferVhdlObj(obj):
|
||||
tipe = obj._val._type
|
||||
else:
|
||||
tipe = obj._type
|
||||
vhd = vhd_enum(tipe)
|
||||
vhd = vhd_enum(tipe)
|
||||
elif isinstance(obj, (int, long)):
|
||||
if obj >= 0:
|
||||
vhd = vhd_nat()
|
||||
@ -1949,7 +1949,7 @@ def maybeNegative(vhd):
|
||||
if isinstance(vhd, vhd_int) and not isinstance(vhd, vhd_nat):
|
||||
return True
|
||||
return False
|
||||
|
||||
|
||||
class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
def __init__(self, tree):
|
||||
@ -1976,7 +1976,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
node.value.vhd = copy(node.target.vhd)
|
||||
node.vhdOri = copy(node.target.vhd)
|
||||
elif isinstance(node.op, (ast.RShift, ast.LShift)):
|
||||
node.value.vhd = vhd_int()
|
||||
node.value.vhd = vhd_int()
|
||||
node.vhdOri = copy(node.target.vhd)
|
||||
else:
|
||||
node.left, node.right = node.target, node.value
|
||||
@ -2044,7 +2044,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
# make it possible to detect loop variable
|
||||
self.tree.vardict[var] = _loopInt(-1)
|
||||
self.generic_visit(node)
|
||||
|
||||
|
||||
def visit_Name(self, node):
|
||||
if node.id in self.tree.vardict:
|
||||
node.obj = self.tree.vardict[node.id]
|
||||
@ -2083,7 +2083,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
if isinstance(left.vhd, vhd_unsigned) and maybeNegative(right.vhd):
|
||||
left.vhd = vhd_signed(left.vhd.size + 1)
|
||||
l, r = left.vhd, right.vhd
|
||||
ls, rs = l.size, r.size
|
||||
ls, rs = l.size, r.size
|
||||
if isinstance(r, vhd_vector) and isinstance(l, vhd_vector):
|
||||
if isinstance(op, (ast.Add, ast.Sub)):
|
||||
s = max(ls, rs)
|
||||
@ -2132,7 +2132,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.generic_visit(node)
|
||||
for test, suite in node.tests:
|
||||
test.vhd = vhd_boolean()
|
||||
|
||||
|
||||
def visit_IfExp(self, node):
|
||||
self.generic_visit(node)
|
||||
node.test.vhd = vhd_boolean()
|
||||
@ -2196,7 +2196,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
elif isinstance(node.vhd, vhd_nat):
|
||||
node.vhd = vhd_int()
|
||||
node.vhdOri = copy(node.vhd)
|
||||
|
||||
|
||||
def visit_While(self, node):
|
||||
self.generic_visit(node)
|
||||
node.test.vhd = vhd_boolean()
|
||||
@ -2211,7 +2211,7 @@ def _annotateTypes(genlist):
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -40,12 +40,12 @@ from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo,
|
||||
_UserVerilogCode, _userCodeMap)
|
||||
|
||||
from myhdl._instance import _Instantiator
|
||||
from myhdl.conversion._misc import (_error, _kind, _context,
|
||||
from myhdl.conversion._misc import (_error, _kind, _context,
|
||||
_ConversionMixin, _Label, _genUniqueSuffix, _isConstant)
|
||||
from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc,
|
||||
from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc,
|
||||
_Ram, _Rom)
|
||||
from myhdl._Signal import _Signal
|
||||
|
||||
|
||||
_converting = 0
|
||||
_profileFunc = None
|
||||
|
||||
@ -53,7 +53,7 @@ def _checkArgs(arglist):
|
||||
for arg in arglist:
|
||||
if not isinstance(arg, (GeneratorType, _Instantiator, _UserVerilogCode)):
|
||||
raise ToVerilogError(_error.ArgType, arg)
|
||||
|
||||
|
||||
def _flatten(*args):
|
||||
arglist = []
|
||||
for arg in args:
|
||||
@ -79,10 +79,10 @@ def _makeDoc(doc, indent=''):
|
||||
|
||||
class _ToVerilogConvertor(object):
|
||||
|
||||
__slots__ = ("name",
|
||||
"timescale",
|
||||
__slots__ = ("name",
|
||||
"timescale",
|
||||
"standard",
|
||||
"prefer_blocking_assignments",
|
||||
"prefer_blocking_assignments",
|
||||
"radix",
|
||||
"header",
|
||||
"no_myhdl_header",
|
||||
@ -124,20 +124,19 @@ class _ToVerilogConvertor(object):
|
||||
|
||||
vpath = name + ".v"
|
||||
vfile = open(vpath, 'w')
|
||||
|
||||
|
||||
### initialize properly ###
|
||||
_genUniqueSuffix.reset()
|
||||
|
||||
siglist, memlist = _analyzeSigs(h.hierarchy)
|
||||
arglist = _flatten(h.top)
|
||||
# print h.top
|
||||
_checkArgs(arglist)
|
||||
genlist = _analyzeGens(arglist, h.absnames)
|
||||
siglist, memlist = _analyzeSigs(h.hierarchy)
|
||||
_annotateTypes(genlist)
|
||||
intf = _analyzeTopFunc(func, *args, **kwargs)
|
||||
intf.name = name
|
||||
doc = _makeDoc(inspect.getdoc(func))
|
||||
|
||||
|
||||
self._convert_filter(h, intf, siglist, memlist, genlist)
|
||||
|
||||
_writeFileHeader(vfile, vpath, self.timescale)
|
||||
@ -157,9 +156,9 @@ class _ToVerilogConvertor(object):
|
||||
|
||||
### clean-up properly ###
|
||||
self._cleanup(siglist)
|
||||
|
||||
|
||||
return h.top
|
||||
|
||||
|
||||
def _cleanup(self, siglist):
|
||||
# clean up signal names
|
||||
for sig in siglist:
|
||||
@ -167,7 +166,7 @@ class _ToVerilogConvertor(object):
|
||||
# sig._name = None
|
||||
# sig._driven = False
|
||||
# sig._read = False
|
||||
|
||||
|
||||
# clean up attributes
|
||||
self.name = None
|
||||
self.standard = '2001'
|
||||
@ -176,13 +175,13 @@ class _ToVerilogConvertor(object):
|
||||
self.header = ""
|
||||
self.no_myhdl_header = False
|
||||
self.no_testbench = False
|
||||
|
||||
|
||||
|
||||
|
||||
def _convert_filter(self, h, intf, siglist, memlist, genlist):
|
||||
# intended to be a entry point for other uses:
|
||||
# intended to be a entry point for other uses:
|
||||
# code checking, optimizations, etc
|
||||
pass
|
||||
|
||||
|
||||
|
||||
toVerilog = _ToVerilogConvertor()
|
||||
|
||||
@ -193,7 +192,7 @@ myhdl_header = """\
|
||||
"""
|
||||
|
||||
def _writeFileHeader(f, fn, ts):
|
||||
vars = dict(filename=fn,
|
||||
vars = dict(filename=fn,
|
||||
version=myhdl.__version__,
|
||||
date=datetime.today().ctime()
|
||||
)
|
||||
@ -290,7 +289,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
|
||||
p = _getSignString(m.elObj)
|
||||
k = 'wire'
|
||||
if m._driven:
|
||||
k = m._driven
|
||||
k = m._driven
|
||||
print >> f, "%s %s%s%s [0:%s-1];" % (k, p, r, m.name, m.depth)
|
||||
print >> f
|
||||
for s in constwires:
|
||||
@ -309,7 +308,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
|
||||
|
||||
def _writeModuleFooter(f):
|
||||
print >> f, "endmodule"
|
||||
|
||||
|
||||
|
||||
def _writeTestBench(f, intf):
|
||||
print >> f, "module tb_%s;" % intf.name
|
||||
@ -336,7 +335,7 @@ def _writeTestBench(f, intf):
|
||||
if to.getvalue():
|
||||
print >> f, " $to_myhdl("
|
||||
print >> f, to.getvalue()[:-2]
|
||||
print >> f, " );"
|
||||
print >> f, " );"
|
||||
print >> f, "end"
|
||||
print >> f
|
||||
print >> f, "%s dut(" % intf.name
|
||||
@ -378,7 +377,7 @@ def _convertGens(genlist, vfile):
|
||||
elif tree.kind == _kind.ALWAYS_DECO:
|
||||
Visitor = _ConvertAlwaysDecoVisitor
|
||||
elif tree.kind == _kind.ALWAYS_SEQ:
|
||||
Visitor = _ConvertAlwaysSeqVisitor
|
||||
Visitor = _ConvertAlwaysSeqVisitor
|
||||
else: # ALWAYS_COMB
|
||||
Visitor = _ConvertAlwaysCombVisitor
|
||||
v = Visitor(tree, blockBuf, funcBuf)
|
||||
@ -417,7 +416,7 @@ opmap = {
|
||||
|
||||
|
||||
class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
|
||||
def __init__(self, tree, buf):
|
||||
self.tree = tree
|
||||
self.buf = buf
|
||||
@ -440,13 +439,13 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
def writeline(self, nr=1):
|
||||
for i in range(nr):
|
||||
self.buf.write("\n%s" % self.ind)
|
||||
|
||||
|
||||
def writeDoc(self, node):
|
||||
assert hasattr(node, 'doc')
|
||||
doc = _makeDoc(node.doc, self.ind)
|
||||
self.write(doc)
|
||||
self.writeline()
|
||||
|
||||
|
||||
def indent(self):
|
||||
self.ind += ' ' * 4
|
||||
|
||||
@ -502,7 +501,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.write(" = %s;" % inival)
|
||||
else:
|
||||
self.write(";")
|
||||
|
||||
|
||||
def writeDeclarations(self):
|
||||
for name, obj in self.tree.vardict.items():
|
||||
self.writeline()
|
||||
@ -566,7 +565,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.write(" %s " % opmap[type(node.op)])
|
||||
self.visit(n)
|
||||
self.write(")")
|
||||
|
||||
|
||||
def visit_UnaryOp(self, node):
|
||||
self.write("(%s" % opmap[type(node.op)])
|
||||
self.visit(node.operand)
|
||||
@ -793,7 +792,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
# ugly hack to detect an orphan "task" call
|
||||
if isinstance(expr, ast.Call) and hasattr(expr, 'tree'):
|
||||
self.write(';')
|
||||
|
||||
|
||||
def visit_IfExp(self, node):
|
||||
self.visit(node.test)
|
||||
self.write(' ? ')
|
||||
@ -912,7 +911,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.dedent()
|
||||
self.writeline()
|
||||
self.write("endcase")
|
||||
|
||||
|
||||
def mapToIf(self, node, *args):
|
||||
first = True
|
||||
for test, suite in node.tests:
|
||||
@ -945,7 +944,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
def visit_Module(self, node, *args):
|
||||
for stmt in node.body:
|
||||
self.visit(stmt)
|
||||
|
||||
|
||||
def visit_ListComp(self, node):
|
||||
pass # do nothing
|
||||
|
||||
@ -1000,7 +999,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.write("$signed({1'b0, ")
|
||||
self.write(s)
|
||||
if addSignBit:
|
||||
self.write("})")
|
||||
self.write("})")
|
||||
|
||||
def visit_Pass(self, node):
|
||||
self.write("// pass")
|
||||
@ -1054,7 +1053,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
def visit_Raise(self, node):
|
||||
self.write("$finish;")
|
||||
|
||||
|
||||
def visit_Return(self, node):
|
||||
self.write("disable %s;" % self.returnLabel)
|
||||
|
||||
@ -1163,9 +1162,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.writeSensitivityList(senslist)
|
||||
self.write(";")
|
||||
|
||||
|
||||
|
||||
class _ConvertAlwaysVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1190,14 +1189,14 @@ class _ConvertAlwaysVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
class _ConvertInitialVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
self.writeDoc(node)
|
||||
self.write("initial begin: %s" % self.tree.name)
|
||||
self.write("initial begin: %s" % self.tree.name)
|
||||
self.indent()
|
||||
self.writeDeclarations()
|
||||
self.visit_stmt(node.body)
|
||||
@ -1209,7 +1208,7 @@ class _ConvertInitialVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
class _ConvertAlwaysCombVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
if toVerilog.prefer_blocking_assignments:
|
||||
@ -1227,9 +1226,9 @@ class _ConvertAlwaysCombVisitor(_ConvertVisitor):
|
||||
self.writeline(2)
|
||||
|
||||
|
||||
|
||||
|
||||
class _ConvertSimpleAlwaysCombVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1245,9 +1244,9 @@ class _ConvertSimpleAlwaysCombVisitor(_ConvertVisitor):
|
||||
self.visit_stmt(node.body)
|
||||
self.writeline(2)
|
||||
|
||||
|
||||
|
||||
class _ConvertAlwaysDecoVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1277,10 +1276,10 @@ def _convertInitVal(reg, init):
|
||||
assert isinstance(init, EnumItemType)
|
||||
v = init._toVerilog()
|
||||
return v
|
||||
|
||||
|
||||
|
||||
class _ConvertAlwaysSeqVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, blockBuf, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, blockBuf)
|
||||
self.funcBuf = funcBuf
|
||||
@ -1319,9 +1318,9 @@ class _ConvertAlwaysSeqVisitor(_ConvertVisitor):
|
||||
self.write("end")
|
||||
self.writeline(2)
|
||||
|
||||
|
||||
|
||||
class _ConvertFunctionVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, funcBuf)
|
||||
self.returnObj = tree.returnObj
|
||||
@ -1336,7 +1335,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
|
||||
obj = self.tree.symdict[name]
|
||||
self.writeline()
|
||||
self.writeDeclaration(obj, name, "input")
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
self.write("function ")
|
||||
self.writeOutputDeclaration()
|
||||
@ -1364,9 +1363,9 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
class _ConvertTaskVisitor(_ConvertVisitor):
|
||||
|
||||
|
||||
def __init__(self, tree, funcBuf):
|
||||
_ConvertVisitor.__init__(self, tree, funcBuf)
|
||||
self.returnLabel = _Label("RETURN")
|
||||
@ -1380,7 +1379,7 @@ class _ConvertTaskVisitor(_ConvertVisitor):
|
||||
dir = (inout and "inout") or (output and "output") or "input"
|
||||
self.writeline()
|
||||
self.writeDeclaration(obj, name, dir)
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
self.write("task %s;" % self.tree.name)
|
||||
self.indent()
|
||||
@ -1410,17 +1409,17 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
|
||||
def __init__(self, tree):
|
||||
self.tree = tree
|
||||
|
||||
|
||||
def visit_FunctionDef(self, node):
|
||||
# don't visit arguments and decorators
|
||||
for stmt in node.body:
|
||||
self.visit(stmt)
|
||||
|
||||
self.visit(stmt)
|
||||
|
||||
def visit_BinOp(self, node):
|
||||
self.visit(node.left)
|
||||
self.visit(node.right)
|
||||
node.signed = node.left.signed or node.right.signed
|
||||
|
||||
|
||||
def visit_BoolOp(self, node):
|
||||
for n in node.values:
|
||||
self.visit(n)
|
||||
@ -1433,20 +1432,20 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
node.obj = int(-1)
|
||||
if isinstance(node.operand, ast.Num):
|
||||
node.signed = True
|
||||
|
||||
|
||||
def visit_Attribute(self, node):
|
||||
if isinstance(node.ctx, ast.Store):
|
||||
self.setAttr(node)
|
||||
else:
|
||||
self.getAttr(node)
|
||||
|
||||
|
||||
def setAttr(self, node):
|
||||
self.visit(node.value)
|
||||
|
||||
def getAttr(self, node):
|
||||
node.signed = False
|
||||
self.visit(node.value)
|
||||
|
||||
|
||||
def visit_Call(self, node):
|
||||
self.generic_visit(node)
|
||||
f = self.getObj(node.func)
|
||||
@ -1457,7 +1456,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
elif hasattr(node, 'tree'):
|
||||
v = _AnnotateTypesVisitor(node.tree)
|
||||
v.visit(node.tree)
|
||||
node.signed = _maybeNegative(node.tree.returnObj)
|
||||
node.signed = _maybeNegative(node.tree.returnObj)
|
||||
|
||||
def visit_Compare(self, node):
|
||||
node.signed = False
|
||||
@ -1466,7 +1465,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
self.visit(n)
|
||||
if n.signed:
|
||||
node.signed = True
|
||||
|
||||
|
||||
def visit_If(self, node):
|
||||
if node.ignore:
|
||||
return
|
||||
@ -1509,13 +1508,13 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
|
||||
node.signed = False
|
||||
self.generic_visit(node)
|
||||
|
||||
|
||||
|
||||
def _annotateTypes(genlist):
|
||||
for tree in genlist:
|
||||
if isinstance(tree, _UserVerilogCode):
|
||||
continue
|
||||
v = _AnnotateTypesVisitor(tree)
|
||||
v.visit(tree)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user