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Initial MEP:107 support.

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All arguments in the top level must be signals, apart from that, you can
access attributes in generators.

--HG--
branch : mep107
This commit is contained in:
Keerthan Jaic 2013-07-03 22:34:21 -04:00
parent 247d0379e2
commit e0b6219bed
5 changed files with 305 additions and 280 deletions
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5
myhdl/_always_comb.py
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@ -31,6 +31,7 @@ from myhdl._util import _isGenFunc, _dedent
from myhdl._cell_deref import _cell_deref
from myhdl._Waiter import _Waiter, _SignalWaiter, _SignalTupleWaiter
from myhdl._instance import _Instantiator
from myhdl._resolverefs import _AttrRefTransformer
class _error:
pass
@ -186,7 +187,9 @@ class _AlwaysComb(_Instantiator):
s = _dedent(s)
tree = ast.parse(s)
# print ast.dump(tree)
v = _SigNameVisitor(symdict)
v = _AttrRefTransformer(self)
v.visit(tree)
v = _SigNameVisitor(self.symdict)
v.visit(tree)
self.inputs = v.inputs
self.outputs = v.outputs

23
myhdl/_extractHierarchy.py
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@ -34,6 +34,7 @@ from myhdl import ExtractHierarchyError, ToVerilogError, ToVHDLError
from myhdl._Signal import _Signal, _isListOfSigs
from myhdl._util import _isGenFunc
from myhdl._misc import _isGenSeq
from myhdl._resolverefs import _resolveRefs
_profileFunc = None
@ -46,8 +47,8 @@ _error.InconsistentToplevel = "Inconsistent top level %s for %s - should be 1"
class _Instance(object):
__slots__ = ['level', 'obj', 'subs', 'sigdict', 'memdict', 'name', 'func', 'argdict']
def __init__(self, level, obj, subs, sigdict, memdict, func, argdict):
__slots__ = ['level', 'obj', 'subs', 'sigdict', 'memdict', 'name', 'func', 'argdict', 'objdict']
def __init__(self, level, obj, subs, sigdict, memdict, func, argdict, objdict=None):
self.level = level
self.obj = obj
self.subs = subs
@ -55,6 +56,8 @@ class _Instance(object):
self.memdict = memdict
self.func = func
self.argdict = argdict
if objdict:
self.objdict = objdict
_memInfoMap = {}
@ -309,9 +312,15 @@ class _HierExtr(object):
arglist = inspect.getargspec(func).args
else:
arglist = []
cellvars = frame.f_code.co_cellvars
for dict in (frame.f_globals, frame.f_locals):
for n, v in dict.items():
symdict = frame.f_globals.copy()
symdict.update(frame.f_locals)
cellvars = []
cellvars.extend(frame.f_code.co_cellvars)
if self.level > 1:
objlist = _resolveRefs(symdict, arg)
cellvars.extend(objlist)
#for dict in (frame.f_globals, frame.f_locals):
for n, v in symdict.items():
# extract signals and memories
# also keep track of whether they are used in generators
# only include objects that are used in generators
@ -336,6 +345,10 @@ class _HierExtr(object):
if elt is sub:
subs.append((n, sub))
inst = _Instance(self.level, arg, subs, sigdict, memdict, func, argdict)
self.hierarchy.append(inst)

26
myhdl/conversion/_analyze.py
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@ -42,6 +42,7 @@ from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode
from myhdl._Signal import _Signal, _WaiterList
from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal
from myhdl._util import _isTupleOfInts, _dedent
from myhdl._resolverefs import _AttrRefTransformer
myhdlObjects = myhdl.__dict__.values()
builtinObjects = __builtin__.__dict__.values()
@ -100,6 +101,10 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
for n, s in sigdict.items():
if s._name is not None:
continue
if '.' in n:
n = n.replace('.', '_')
while n in sigdict:
n = n + '_'
if isinstance(s, _SliceSignal):
continue
s._name = _makeName(n, prefixes)
@ -158,21 +163,24 @@ def _analyzeGens(top, absnames):
if f.func_code.co_freevars:
for n, c in zip(f.func_code.co_freevars, f.func_closure):
obj = _cell_deref(c)
tree.symdict[n] = obj
# currently, only intbv as automatic nonlocals (until Python 3.0)
if isinstance(obj, intbv):
tree.nonlocaldict[n] = obj
tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()
v = _AttrRefTransformer(tree)
v.visit(tree)
v = _FirstPassVisitor(tree)
v.visit(tree)
if isinstance(g, _AlwaysComb):
objs = [tree.symdict[objname] for objname in tree.objlist]
for obj in objs:
if not ( isinstance(obj, (int, long, EnumType,_Signal)) or \
_isMem(obj) or _isTupleOfInts(obj)
):
info = "File %s, line %s: " % (tree.sourcefile, tree.lineoffset)
print type(obj)
raise ConversionError(_error.UnsupportedType, n, info)
tree.symdict[n] = obj
# currently, only intbv as automatic nonlocals (until Python 3.0)
if isinstance(obj, intbv):
tree.nonlocaldict[n] = obj
tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()
v = _FirstPassVisitor(tree)
v.visit(tree)
if isinstance(g, _AlwaysComb):
v = _AnalyzeAlwaysCombVisitor(tree, g.senslist)
elif isinstance(g, _AlwaysSeq):
v = _AnalyzeAlwaysSeqVisitor(tree, g.senslist, g.reset, g.sigregs, g.varregs)
@ -192,6 +200,8 @@ def _analyzeGens(top, absnames):
tree.nonlocaldict = {}
tree.callstack = []
tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()
v = _AttrRefTransformer(tree)
v.visit(tree)
v = _FirstPassVisitor(tree)
v.visit(tree)
v = _AnalyzeBlockVisitor(tree)

4
myhdl/conversion/_toVHDL.py
View File

@ -150,11 +150,11 @@ class _ToVHDLConvertor(object):
_constDict.clear()
_extConstDict.clear()
siglist, memlist = _analyzeSigs(h.hierarchy, hdl='VHDL')
arglist = _flatten(h.top)
# print h.top
_checkArgs(arglist)
genlist = _analyzeGens(arglist, h.absnames)
siglist, memlist = _analyzeSigs(h.hierarchy, hdl='VHDL')
# print h.top
_annotateTypes(genlist)
### infer interface

3
myhdl/conversion/_toVerilog.py
View File

@ -128,14 +128,13 @@ class _ToVerilogConvertor(object):
### initialize properly ###
_genUniqueSuffix.reset()
siglist, memlist = _analyzeSigs(h.hierarchy)
arglist = _flatten(h.top)
# print h.top
_checkArgs(arglist)
genlist = _analyzeGens(arglist, h.absnames)
siglist, memlist = _analyzeSigs(h.hierarchy)
_annotateTypes(genlist)
intf = _analyzeTopFunc(func, *args, **kwargs)
intf.name = name
doc = _makeDoc(inspect.getdoc(func))
self._convert_filter(h, intf, siglist, memlist, genlist)