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https://github.com/myhdl/myhdl.git
synced 2024-12-14 07:44:38 +08:00
first VHDL example that works
This commit is contained in:
jand
parent
a6b77fd084
commit
e14c01d30a
@ -54,8 +54,7 @@ class _PosedgeWaiterList(_WaiterList):
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def _toVerilog(self):
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return "posedge %s" % self.sig._name
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def _toVHDL(self):
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return self.sig._name
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#return "rising_edge(%s)" % self.sig._name
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return "rising_edge(%s)" % self.sig._name
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class _NegedgeWaiterList(_WaiterList):
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def __init__(self, sig):
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@ -63,8 +62,7 @@ class _NegedgeWaiterList(_WaiterList):
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def _toVerilog(self):
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return "negedge %s" % self.sig._name
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def _toVHDL(self):
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return self.sig._name
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#return "falling_edge(%s)" % self.sig._name
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return "falling_edge(%s)" % self.sig._name
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def posedge(sig):
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@ -116,10 +116,9 @@ from _instance import instance
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from _enum import enum, EnumType, EnumItemType
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from _traceSignals import traceSignals
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from _toVerilog._convert import toVerilog
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try:
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from _toVHDL._convert import toVHDL
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except:
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toVHDL = None
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from _toVHDL._convert import toVHDL
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__all__ = ["bin",
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"concat",
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@ -48,7 +48,8 @@ from myhdl._always import _Always
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from myhdl._toVerilog import _error, _access, _kind,_context, \
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_ToVerilogMixin, _Label
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from myhdl._toVerilog._analyze import _analyzeSigs, _analyzeGens, _analyzeTopFunc, \
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_Ram, _Rom, _EdgeDetector
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_Ram, _Rom
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from myhdl._Signal import _WaiterList
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_converting = 0
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_profileFunc = None
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@ -134,6 +135,10 @@ toVHDL = _ToVHDLConvertor()
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def _writeModuleHeader(f, intf):
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print >> f, "library IEEE;"
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print >> f, "use IEEE.std_logic_1164.all;"
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print >> f, "use IEEE.numeric_std.all;"
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print >> f
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print >> f, "entity %s is" % intf.name
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if intf.argnames:
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print >> f, " port ("
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@ -170,7 +175,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
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)
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# the following line implements initial value assignments
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# print >> f, "%s %s%s = %s;" % (s._driven, r, s._name, int(s._val))
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print >> f, "signal %s %s%s;" % (s._name, p, r)
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print >> f, "signal %s: %s%s;" % (s._name, p, r)
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elif s._read:
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# the original exception
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# raise ToVerilogError(_error.UndrivenSignal, s._name)
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@ -185,9 +190,11 @@ def _writeSigDecls(f, intf, siglist, memlist):
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continue
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r = _getRangeString(m.elObj)
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print >> f, "reg %s%s [0:%s-1];" % (r, m.name, m.depth)
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print >> f
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for s in constwires:
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print >> f, "%s <= %s;" % (s._name, int(s._val))
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print >> f
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print >> f, "begin"
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print >> f
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def _writeModuleFooter(f):
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@ -463,7 +470,6 @@ class _ConvertVisitor(_ToVerilogMixin):
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else:
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self.write(' = ')
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node.expr.target = self.getObj(node.nodes[0])
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print node.expr.target
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self.visit(node.expr)
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self.write(';')
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@ -559,6 +565,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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if op == "==":
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op = "="
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self.write(" %s " % op)
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print context
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self.visit(code, context)
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self.write(")")
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@ -726,14 +733,21 @@ class _ConvertVisitor(_ToVerilogMixin):
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ifstring = "elsif"
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self.writeline()
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self.write(ifstring)
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self.visit(test)
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self.visit(test, _context.BOOLEAN)
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self.write(" then")
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self.indent()
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self.visit(suite)
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self.dedent()
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if node.else_:
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self.writeline()
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self.write("else")
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edges = self.getEdge(node.else_)
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if edges is not None:
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edgeTests = [e._toVHDL() for e in edges]
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self.write("elsif ")
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self.write("or ".join(edgeTests))
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self.write(" then")
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else:
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self.write("else")
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self.indent()
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self.visit(node.else_)
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self.dedent()
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@ -765,13 +779,19 @@ class _ConvertVisitor(_ToVerilogMixin):
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elif n in self.ast.symdict:
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obj = self.ast.symdict[n]
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if isinstance(obj, bool):
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s = "%s" % int(obj)
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s = "'%s'" % int(obj)
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elif isinstance(obj, (int, long)):
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self.writeIntSize(obj)
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s = str(obj)
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elif isinstance(obj, Signal):
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addSignBit = isMixedExpr
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s = str(obj)
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if context == _context.PRINT:
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s = "integer'image(to_integer(%s))" % str(obj)
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elif context == _context.BOOLEAN and \
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obj._type is bool:
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s = "%s = '1'" % str(obj)
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else:
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addSignBit = isMixedExpr
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s = str(obj)
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elif _isMem(obj):
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m = _getMemInfo(obj)
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assert m.name
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@ -796,13 +816,11 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.write("// pass")
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def handlePrint(self, node):
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self.write('$display(')
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assert len(node.nodes) == 1
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self.write('report ')
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s = node.nodes[0]
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self.visit(s, _context.PRINT)
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for s in node.nodes[1:]:
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self.write(', , ')
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self.visit(s, _context.PRINT)
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self.write(');')
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self.write(';')
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def visitPrint(self, node, *args):
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self.handlePrint(node)
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@ -912,7 +930,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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yieldObj = self.getObj(node.value)
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if isinstance(yieldObj, delay):
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self.write("for ")
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elif isinstance(yieldObj, _EdgeDetector):
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elif isinstance(yieldObj, _WaiterList):
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self.write("until ")
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else:
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self.write("on ")
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@ -954,7 +972,7 @@ class _ConvertInitialVisitor(_ConvertVisitor):
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self.funcBuf = funcBuf
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def visitFunction(self, node, *args):
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self.write("%s: process begin" % self.ast.name)
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self.write("%s: process is\nbegin" % self.ast.name)
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self.indent()
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self.writeDeclarations()
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self.visit(node.code)
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@ -1012,13 +1030,45 @@ class _ConvertAlwaysDecoVisitor(_ConvertVisitor):
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self.funcBuf = funcBuf
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def visitFunction(self, node, *args):
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self.write("%s: process (" % self.ast.name)
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assert self.ast.senslist
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for e in self.ast.senslist[:-1]:
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self.write(e._toVHDL())
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senslist = self.ast.senslist
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first = senslist[0]
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if isinstance(first, _WaiterList):
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bt = _WaiterList
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elif isinstance(first, Signal):
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bt = Signal
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elif isinstance(first, delay):
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bt = delay
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assert bt
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for e in senslist:
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if not isinstance(e, bt):
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self.raiseError(node, "base type error in sensitivity list")
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if len(senslist) >= 2 and bt == _WaiterList:
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ifnode = node.code.nodes[0]
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assert isinstance(ifnode, astNode.If)
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asyncEdges = []
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for test, suite in ifnode.tests:
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e = self.getEdge(test)
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if e is None:
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self.raiseError(node, "no edge test")
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asyncEdges.append(e)
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if ifnode.else_ is None:
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self.raiseError(node, "no else test")
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edges = []
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for s in senslist:
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for e in asyncEdges:
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if s is e:
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break
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else:
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edges.append(s)
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ifnode.else_.edge = edges
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senslist = [s.sig for s in senslist]
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self.write("%s: process (" % self.ast.name)
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for e in senslist[:-1]:
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self.write(e)
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self.write(', ')
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self.write(self.ast.senslist[-1]._toVHDL())
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self.write(")")
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self.write(senslist[-1])
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self.write(") is")
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self.writeline()
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self.write("begin")
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self.indent()
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@ -102,6 +102,16 @@ class _ToVerilogMixin(object):
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return node.kind
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return None
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def getEdge(self, node):
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if hasattr(node, 'edge'):
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return node.edge
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return None
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def getValue(self, node):
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if hasattr(node, 'value'):
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return node.value
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return None
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def getVal(self, node):
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val = eval(_unparse(node), self.ast.symdict)
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return val
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@ -45,6 +45,7 @@ from myhdl._delay import delay
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from myhdl._toVerilog import _error, _access, _kind, _context, \
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_ToVerilogMixin, _Label
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from myhdl._extractHierarchy import _isMem, _UserDefinedVerilog
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from myhdl._Signal import _WaiterList
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myhdlObjects = myhdl.__dict__.values()
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builtinObjects = __builtin__.__dict__.values()
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@ -129,7 +130,7 @@ def _analyzeGens(top, absnames):
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s = re.sub(r"@.*", "", s)
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s = s.lstrip()
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ast = compiler.parse(s)
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#print ast
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print ast
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ast.sourcefile = inspect.getsourcefile(f)
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ast.lineoffset = inspect.getsourcelines(f)[1]-1
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ast.symdict = f.func_globals.copy()
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@ -157,7 +158,7 @@ def _analyzeGens(top, absnames):
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s = re.sub(r"@.*", "", s)
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s = s.lstrip()
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ast = compiler.parse(s)
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#print ast
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print ast
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ast.sourcefile = inspect.getsourcefile(f)
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ast.lineoffset = inspect.getsourcelines(f)[1]-1
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ast.symdict = f.f_globals.copy()
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@ -270,6 +271,7 @@ class _NotSupportedVisitor(_ToVerilogMixin):
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if node.dest is not None:
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self.raiseError(node, _error.NotSupported, "printing to a file with >> syntax")
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self.visitChildNodes(node, *args)
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self.ast.hasPrint = True
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visitPrint = visitPrintnl
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@ -308,8 +310,8 @@ class ReferenceStack(list):
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return False
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# auxiliary types to aid type checking
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class _EdgeDetector(object):
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pass
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## class _EdgeDetector(object):
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## pass
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class _Ram(object):
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__slots__ = ['elObj', 'depth']
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@ -339,6 +341,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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ast.kind = None
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ast.isGen = False
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ast.hasRom = False
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ast.hasPrint = False
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self.ast = ast
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self.labelStack = []
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self.refStack = ReferenceStack()
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@ -540,6 +543,11 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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if n.signed:
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node.signed = True
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op, arg = node.ops[0]
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node.expr.target = self.getObj(arg)
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print type(self.getObj(arg))
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arg.target = self.getObj(node.expr)
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print type(self.getObj(node.expr))
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print arg.target._type
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# detect specialized case for the test
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if op == '==' and isinstance(node.expr, astNode.Name):
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n = node.expr.name
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@ -549,21 +557,12 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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# check whether it can be part of an edge check
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elif n in self.ast.sigdict:
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sig = self.ast.sigdict[n]
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if isinstance(arg.obj, astNode.Const):
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v = arg.obj.value
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if value == 0:
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v = self.getValue(arg)
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if v is not None:
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if v == 0:
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node.edge = sig.negedge
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elif value == 1:
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elif v == 1:
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node.edge = sig.posedge
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elif isinstance(arg.obj, astNode.Name):
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c = arg.obj.name
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if c in self.ast.symdict:
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a = self.ast.symdict[n]
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if isinstance(a, int):
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if a == 0:
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node.edge = sig.negedge
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elif a == 1:
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node.edge = sig.posedge
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def visitConst(self, node, *args):
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@ -605,8 +604,10 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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node.signed = False
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obj = self.ast.symdict[node.expr.name]
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if isinstance(obj, Signal):
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if node.attrname in ('posedge', 'negedge'):
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node.obj = _EdgeDetector()
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if node.attrname == 'posedge':
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node.obj = obj.posedge
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elif node.attrname == 'negedge':
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node.obj = obj.negedge
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elif node.attrname == 'val':
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node.obj = obj.val
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elif isinstance(obj, EnumType):
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@ -698,11 +699,14 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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if isTupleOfInts(node.obj):
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node.obj = _Rom(node.obj)
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self.ast.hasRom = True
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elif isinstance(node.obj, int):
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node.value = node.obj
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elif n in __builtin__.__dict__:
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node.obj = __builtin__.__dict__[n]
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else:
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pass
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node.signed = _isNegative(node.obj)
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node.target = node.obj
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def visitReturn(self, node, *args):
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self.raiseError(node, _error.NotSupported, "return statement")
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@ -763,13 +767,16 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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self.ast.isGen = True
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n = node.value
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self.visit(n)
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senslist = []
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if isinstance(n, astNode.Tuple):
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for n in n.nodes:
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if not type(n.obj) in (Signal, _EdgeDetector):
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if not isinstance(n.obj, (Signal, _WaiterList)):
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self.raiseError(node, _error.UnsupportedYield)
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senslist.append(n.obj)
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else:
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if not type(n.obj) in (Signal, _EdgeDetector, delay):
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if not isinstance(n.obj, (Signal, _WaiterList, delay)):
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self.raiseError(node, _error.UnsupportedYield)
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senlist = [n.obj]
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class _AnalyzeBlockVisitor(_AnalyzeVisitor):
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