FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity

basic issue templates

Browse Source
This commit is contained in:
Keerthan Jaic 2019-02-02 23:19:18 -05:00
parent f696b82ca5
commit e25bf37681
3 changed files with 34 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
.github/ISSUE_TEMPLATE/bug_report.md vendored Normal file
View File

@ -0,0 +1,15 @@
---
name: Bug report
about: Create a report to help us improve
title: ''
labels: bug
assignees: ''
---
Summary
## System information
```
MyHDL Version:
Python Version:
```

9
.github/ISSUE_TEMPLATE/feature_request.md vendored Normal file
View File

@ -0,0 +1,9 @@
---
name: Feature request
about: Suggest an enhancement
title: ''
labels: enhancement
assignees: ''
---

10
.github/ISSUE_TEMPLATE/usage_help.md vendored Normal file
View File

@ -0,0 +1,10 @@
---
name: Usage question
about: Guidance on using MyHDL
title: ''
labels: question
assignees: ''
---
Please refer to our [discourse](http://discourse.myhdl.org/) or <https://gitter.im/myhdl/myhdl>