mirror of
https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
use the Block methods and code cleanup
This commit is contained in:
Christopher Felton
parent
6999886051
commit
e2f559c883
@ -1,48 +1,47 @@
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from __future__ import absolute_import
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import sys
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from myhdl import (block, Signal, ResetSignal, intbv, always_seq,
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instance, delay, StopSimulation, )
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import myhdl
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from myhdl import *
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from myhdl import ConversionError
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from myhdl.conversion._misc import _error
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from myhdl.conversion import analyze, verify
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class MyIntf(object):
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def __init__(self):
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self.x = Signal(intbv(2,min=0,max=16))
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self.y = Signal(intbv(3,min=0,max=18))
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self.x = Signal(intbv(2, min=0, max=16))
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self.y = Signal(intbv(3, min=0, max=18))
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@block
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def m_one_level(clock,reset,ia,ib):
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def one_level(clock, reset, ia, ib):
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@always_seq(clock.posedge,reset=reset)
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@always_seq(clock.posedge, reset=reset)
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def rtl():
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ia.x.next = ib.x + 1
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ia.y.next = ib.y + 1
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return rtl
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@block
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def m_two_level(clock,reset,ia,ib):
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ic,ie = (MyIntf(),MyIntf(),)
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g_one = m_one_level(clock,reset,ic,ie)
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@always_seq(clock.posedge,reset=reset)
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@block
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def two_level(clock, reset, ia, ib):
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ic, ie = MyIntf(), MyIntf()
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one_inst = one_level(clock, reset, ic, ie)
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@always_seq(clock.posedge, reset=reset)
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def rtl():
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ia.x.next = ib.x + ic.x
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ia.y.next = ib.y + ic.y
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return g_one, rtl
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return one_inst, rtl
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@block
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def c_testbench_one():
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clock = Signal(bool(0))
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reset = ResetSignal(0,active=0,async=True)
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ia = MyIntf()
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ib = MyIntf()
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reset = ResetSignal(0, active=0, async=True)
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ia, ib = MyIntf(), MyIntf()
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tb_dut = m_one_level(clock,reset,ia,ib)
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tb_dut = one_level(clock, reset, ia, ib)
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@instance
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def tb_clk():
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@ -62,19 +61,19 @@ def c_testbench_one():
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yield clock.posedge
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assert ia.x == 3
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assert ia.y == 4
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print("%d %d %d %d"%(ia.x,ia.y,ib.x,ib.y))
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print("%d %d %d %d" % (ia.x, ia.y, ib.x, ib.y))
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raise StopSimulation
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return tb_dut, tb_clk, tb_stim
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@block
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def c_testbench_two():
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clock = Signal(bool(0))
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reset = ResetSignal(0,active=0,async=True)
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ia = MyIntf()
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ib = MyIntf()
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reset = ResetSignal(0, active=0, async=True)
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ia, ib = MyIntf(), MyIntf()
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tb_dut = m_two_level(clock,reset,ia,ib)
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tb_dut = two_level(clock, reset, ia, ib)
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@instance
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def tb_clk():
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@ -94,36 +93,33 @@ def c_testbench_two():
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yield clock.posedge
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assert ia.x == 5
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assert ia.y == 7
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print("%d %d %d %d"%(ia.x,ia.y,ib.x,ib.y))
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print("%d %d %d %d" % (ia.x, ia.y, ib.x, ib.y))
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raise StopSimulation
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return tb_dut, tb_clk, tb_stim
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def test_one_level_analyze():
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clock = Signal(bool(0))
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reset = ResetSignal(0,active=0,async=True)
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ia = MyIntf()
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ib = MyIntf()
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analyze(m_one_level(clock,reset,ia,ib))
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reset = ResetSignal(0, active=0, async=True)
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ia, ib = MyIntf(), MyIntf()
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inst = one_level(clock, reset, ia, ib)
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assert inst.analyze_convert() == 0
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def test_one_level_verify():
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assert verify(c_testbench_one()) == 0
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inst = c_testbench_one()
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assert inst.verify_convert() == 0
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def test_two_level_analyze():
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clock = Signal(bool(0))
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reset = ResetSignal(0,active=0,async=True)
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ia = MyIntf()
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ib = MyIntf()
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analyze(m_two_level(clock,reset,ia,ib))
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reset = ResetSignal(0, active=0, async=True)
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ia, ib = MyIntf(), MyIntf()
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inst = two_level(clock, reset, ia, ib)
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assert inst.analyze_convert() == 0
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def test_two_level_verify():
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assert verify(c_testbench_two()) == 0
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if __name__ == '__main__':
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print(sys.argv[1])
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verify.simulator = analyze.simulator = sys.argv[1]
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Simulation(c_testbench_one()).run()
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Simulation(c_testbench_two()).run()
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print(verify(c_testbench_one))
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print(verify(c_testbench_two))
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inst = c_testbench_two()
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assert inst.verify_convert() == 0
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@ -1,23 +1,21 @@
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from __future__ import absolute_import
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import sys
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from myhdl import (block, Signal, ResetSignal, intbv, always_seq, always_comb,
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instance, delay, StopSimulation, )
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import myhdl
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from myhdl import *
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from myhdl.conversion import analyze,verify
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class Intf(object):
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def __init__(self):
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self.x = Signal(intbv(1,min=-1111,max=1111))
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self.y = Signal(intbv(2,min=-2211,max=2211))
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self.z = Signal(intbv(3,min=-3311,max=3311))
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self.x = Signal(intbv(1, min=-1111, max=1111))
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self.y = Signal(intbv(2, min=-2211, max=2211))
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self.z = Signal(intbv(3, min=-3311, max=3311))
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@block
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def m_modify(clock,reset,a):
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def modify(clock, reset, a):
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intfa = Intf()
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@always_seq(clock.posedge,reset=reset)
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@always_seq(clock.posedge, reset=reset)
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def rtl_inc():
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intfa.x.next = intfa.x + 1
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intfa.y.next = intfa.y + 2
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@ -29,17 +27,18 @@ def m_modify(clock,reset,a):
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a.y.next = intfa.y + 2
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a.z.next = intfa.z + 3
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return rtl_inc,rtl_add
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return rtl_inc, rtl_add
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@block
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def m_test_intf(clock,reset,a,b,c):
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def use_interfaces(clock, reset, a, b, c):
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intfa = Intf()
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intfaa = Intf()
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gen_mod = m_modify(clock,reset,intfaa)
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mod_inst = modify(clock, reset, intfaa)
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@always_seq(clock.posedge,reset=reset)
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@always_seq(clock.posedge, reset=reset)
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def rtl_inc():
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intfa.x.next = intfa.x - 1
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intfa.y.next = intfa.y - 2
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@ -59,12 +58,12 @@ def m_test_intf(clock,reset,a,b,c):
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a.y.next = intfaa.y + 2
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a.z.next = intfaa.z + 3
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return gen_mod,rtl_inc,rtl_combine
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return mod_inst, rtl_inc, rtl_combine
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@block
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def name_conflict_after_replace(clock, reset, a, a_x):
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a_x_0 = [Signal(intbv(0)[len(a_x):]) for i in range(8)]
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a_x_0 = [Signal(intbv(0)[len(a_x):]) for _ in range(8)]
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@always_seq(clock.posedge, reset=reset)
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def logic():
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@ -79,15 +78,17 @@ def test_name_conflict_after_replace():
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reset = ResetSignal(0, active=0, async=False)
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a = Intf()
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a_x = Signal(intbv(0)[len(a.x):])
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assert conversion.analyze(name_conflict_after_replace(clock, reset, a, a_x)) == 0
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inst = name_conflict_after_replace(clock, reset, a, a_x)
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assert inst.analyze_convert() == 0
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@block
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def c_testbench():
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clock = Signal(bool(0))
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reset = ResetSignal(0, active=0, async=False)
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a,b,c = (Intf(),Intf(),Intf(),)
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a, b, c = Intf(), Intf(), Intf()
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tb_dut = m_test_intf(clock,reset,a,b,c)
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tb_dut = use_interfaces(clock, reset, a, b, c)
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@instance
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def tb_clk():
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@ -104,25 +105,24 @@ def c_testbench():
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reset.next = True
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yield delay(33)
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for ii in range(17):
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print("a: x=%d y=%d z=%d"%(a.x,a.y,a.z))
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print("b: x=%d y=%d z=%d"%(b.x,b.y,b.z))
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print("c: x=%d y=%d z=%d"%(c.x,c.y,c.z))
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print("a: x=%d y=%d z=%d" % (a.x, a.y, a.z,))
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print("b: x=%d y=%d z=%d" % (b.x, b.y, b.z,))
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print("c: x=%d y=%d z=%d" % (c.x, c.y, c.z,))
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yield clock.posedge
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raise StopSimulation
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return tb_dut,tb_clk,tb_stim
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return tb_dut, tb_clk, tb_stim
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def test_name_conflicts_analyze():
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clock = Signal(bool(0))
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reset = ResetSignal(0, active=0, async=False)
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a,b,c = (Intf(),Intf(),Intf(),)
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analyze(m_test_intf(clock,reset,a,b,c))
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a, b, c = Intf(), Intf(), Intf()
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inst = use_interfaces(clock, reset, a, b, c)
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assert inst.analyze_convert() == 0
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def test_name_conflicts_verify():
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assert verify(c_testbench()) == 0
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if __name__ == '__main__':
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verify.simulator = analyze.simulator = sys.argv[1]
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Simulation(c_testbench()).run()
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print(verify(c_testbench))
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inst = c_testbench()
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assert inst.verify_convert() == 0
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@ -2,30 +2,26 @@ from __future__ import absolute_import
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import sys
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import pytest
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import myhdl
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from myhdl import *
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from myhdl import ConversionError
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from myhdl.conversion._misc import _error
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from myhdl.conversion import analyze, verify
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import myhdl
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from myhdl import *
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from myhdl import (block, Signal, ResetSignal, intbv, always_comb, always_seq,
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instance, delay, StopSimulation, )
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class Intf1:
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def __init__(self, x):
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self.x = Signal(intbv(0, min=x.min, max=x.max))
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class Intf2:
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def __init__(self, y):
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self.y = Signal(intbv(0, min=y.min, max=y.max))
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class ZBus:
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def __init__(self, z):
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self.z = Signal(intbv(0, min=z.min, max=z.max))
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class Intf3:
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def __init__(self, z):
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self.z = ZBus(z)
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@ -36,6 +32,7 @@ class IntfWithConstant1:
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self.const1 = 707
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self.const2 = 3
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class IntfWithConstant2:
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def __init__(self):
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self.a = 9
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@ -45,50 +42,63 @@ class IntfWithConstant2:
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@block
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def m_assign(y, x):
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def assign(y, x):
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@always_comb
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def assign():
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def beh_assign():
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y.next = x
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return assign
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return beh_assign
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@block
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def m_top_assign(x,y,z):
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"""
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This module does not test top-level interfaces,
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it only tests intermediate interfaces.
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"""
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i1,i2 = Intf1(x), Intf2(y)
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ga1 = m_assign(x, i1.x) # x = i1.x
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ga2 = m_assign(i2.y, y) # i2.y = y
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gm1 = m_assign_intf(i1, i2)
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return ga1, ga2, gm1
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@block
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def m_assign_intf(x, y):
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def assign_intf(x, y):
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@always_comb
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def rtl():
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x.x.next = y.y
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return rtl
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@block
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def top_assign(x, y, z):
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"""
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This module does not test top-level interfaces,
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it only tests intermediate interfaces.
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"""
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i1, i2 = Intf1(x), Intf2(y)
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inst1 = assign(x, i1.x) # x = i1.x
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inst2 = assign(i2.y, y) # i2.y = y
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inst3 = assign_intf(i1, i2)
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return myhdl.instances()
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@block
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def c_testbench_one():
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x,y,z = [Signal(intbv(0, min=-8, max=8))
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for _ in range(3)]
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x, y, z = [Signal(intbv(0, min=-8, max=8))
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for _ in range(3)]
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tb_dut = top_assign(x, y, z)
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tb_dut = m_top_assign(x,y,z)
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@instance
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def tb_stim():
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y.next = 3
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yield delay(10)
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print("x: %d" % (x))
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print("x: %d" % (x,))
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assert x == 3
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return tb_dut, tb_stim
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@block
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def m_top_multi_comb(x,y,z):
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def multi_comb(x, y, z):
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@always_comb
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def rtl():
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x.x.next = y.y + z.z.z
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return rtl
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@block
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def top_multi_comb(x, y, z):
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"""
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This module does not test top-level interfaces,
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it only tests intermediate interfaces.
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@ -97,34 +107,29 @@ def m_top_multi_comb(x,y,z):
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x.assign(intf[0].x)
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intf[1].y.assign(y)
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intf[2].z.z.assign(z)
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gm = m_multi_comb(*intf)
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return gm
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inst = multi_comb(*intf)
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return inst
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@block
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def m_multi_comb(x, y, z):
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@always_comb
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def rtl():
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x.x.next = y.y + z.z.z
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return rtl
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@block
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def c_testbench_two():
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x,y,z = [Signal(intbv(0, min=-8, max=8))
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for _ in range(3)]
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tb_dut = m_top_multi_comb(x,y,z)
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x, y, z = [Signal(intbv(0, min=-8, max=8))
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for _ in range(3)]
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tb_dut = top_multi_comb(x, y, z)
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@instance
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def tb_stim():
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y.next = 3
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z.next = 2
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yield delay(10)
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print("x: %d" % (x))
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print("x: %d" % (x,))
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assert x == 5
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return tb_dut, tb_stim
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@block
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def m_top_const(clock, reset, x, y, intf):
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def top_const(clock, reset, x, y, intf):
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@always_seq(clock.posedge, reset=reset)
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def rtl1():
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@ -138,6 +143,7 @@ def m_top_const(clock, reset, x, y, intf):
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return rtl1, rtl2
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@block
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def c_testbench_three():
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"""
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@ -150,7 +156,7 @@ def c_testbench_three():
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y = Signal(intbv(4, min=-200, max=200))
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intf = IntfWithConstant2()
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tbdut = m_top_const(clock, reset, x, y, intf)
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tbdut = top_const(clock, reset, x, y, intf)
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@instance
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def tbclk():
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@ -174,31 +180,40 @@ def c_testbench_three():
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return tbdut, tbclk, tbstim
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def test_one_analyze():
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x,y,z = [Signal(intbv(0, min=-8, max=8))
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for _ in range(3)]
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x, y, z = [Signal(intbv(0, min=-8, max=8))
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for _ in range(3)]
|
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# fool name check in convertor
|
||||
# to be reviewed
|
||||
x._name = 'x'
|
||||
y._name = 'y'
|
||||
z._name = 'z'
|
||||
analyze(m_top_assign(x, y, z))
|
||||
inst = top_assign(x, y, z)
|
||||
assert inst.analyze_convert() == 0
|
||||
|
||||
|
||||
def test_one_verify():
|
||||
assert verify(c_testbench_one()) == 0
|
||||
inst = c_testbench_one()
|
||||
assert inst.verify_convert() == 0
|
||||
|
||||
|
||||
def test_two_analyze():
|
||||
x,y,z = [Signal(intbv(0, min=-8, max=8))
|
||||
for _ in range(3)]
|
||||
# fool name check in convertor
|
||||
x, y, z = [Signal(intbv(0, min=-8, max=8))
|
||||
for _ in range(3)]
|
||||
# fool name check in converter
|
||||
# to be reviewed
|
||||
x._name = 'x'
|
||||
y._name = 'y'
|
||||
z._name = 'z'
|
||||
analyze(m_top_multi_comb(x, y, z))
|
||||
inst = top_multi_comb(x, y, z)
|
||||
assert inst.analyze_convert() == 0
|
||||
|
||||
|
||||
def test_two_verify():
|
||||
assert verify(c_testbench_two()) == 0
|
||||
inst = c_testbench_two()
|
||||
assert inst.verify_convert() == 0
|
||||
|
||||
|
||||
def test_three_analyze():
|
||||
clock = Signal(bool(0))
|
||||
@ -206,25 +221,10 @@ def test_three_analyze():
|
||||
x = Signal(intbv(3, min=-5000, max=5000))
|
||||
y = Signal(intbv(4, min=-200, max=200))
|
||||
intf = IntfWithConstant2()
|
||||
analyze(m_top_const(clock, reset, x, y, intf))
|
||||
inst = top_const(clock, reset, x, y, intf)
|
||||
assert inst.analyze_convert() == 0
|
||||
|
||||
|
||||
def test_three_verify():
|
||||
assert verify(c_testbench_three()) == 0
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
print(sys.argv[1])
|
||||
verify.simulator = analyze.simulator = sys.argv[1]
|
||||
print("*** verify myhdl simulation")
|
||||
Simulation(c_testbench_one()).run()
|
||||
Simulation(c_testbench_two()).run()
|
||||
Simulation(c_testbench_three()).run()
|
||||
print("*** myhdl simulation ok")
|
||||
print("")
|
||||
|
||||
print("*** myhdl verify conversion")
|
||||
print(verify(c_testbench_one))
|
||||
print(verify(c_testbench_two))
|
||||
print(verify(c_testbench_three))
|
||||
print("*** myhdl conversion ok")
|
||||
print("")
|
||||
inst = c_testbench_three()
|
||||
assert inst.verify_convert() == 0
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user