From e2f559c883b20960b8fb4ee5f329c07380bd1e91 Mon Sep 17 00:00:00 2001 From: Christopher Felton Date: Fri, 3 Jun 2016 11:05:05 -0500 Subject: [PATCH] use the Block methods and code cleanup --- .../conversion/general/test_interfaces1.py | 86 +++++----- .../conversion/general/test_interfaces2.py | 62 +++---- .../conversion/general/test_interfaces3.py | 152 +++++++++--------- 3 files changed, 148 insertions(+), 152 deletions(-) diff --git a/myhdl/test/conversion/general/test_interfaces1.py b/myhdl/test/conversion/general/test_interfaces1.py index eda454f4..f79e9936 100644 --- a/myhdl/test/conversion/general/test_interfaces1.py +++ b/myhdl/test/conversion/general/test_interfaces1.py @@ -1,48 +1,47 @@ from __future__ import absolute_import -import sys +from myhdl import (block, Signal, ResetSignal, intbv, always_seq, + instance, delay, StopSimulation, ) -import myhdl -from myhdl import * -from myhdl import ConversionError -from myhdl.conversion._misc import _error -from myhdl.conversion import analyze, verify class MyIntf(object): def __init__(self): - self.x = Signal(intbv(2,min=0,max=16)) - self.y = Signal(intbv(3,min=0,max=18)) + self.x = Signal(intbv(2, min=0, max=16)) + self.y = Signal(intbv(3, min=0, max=18)) + @block -def m_one_level(clock,reset,ia,ib): +def one_level(clock, reset, ia, ib): - @always_seq(clock.posedge,reset=reset) + @always_seq(clock.posedge, reset=reset) def rtl(): ia.x.next = ib.x + 1 ia.y.next = ib.y + 1 return rtl -@block -def m_two_level(clock,reset,ia,ib): - ic,ie = (MyIntf(),MyIntf(),) - g_one = m_one_level(clock,reset,ic,ie) - @always_seq(clock.posedge,reset=reset) +@block +def two_level(clock, reset, ia, ib): + + ic, ie = MyIntf(), MyIntf() + one_inst = one_level(clock, reset, ic, ie) + + @always_seq(clock.posedge, reset=reset) def rtl(): ia.x.next = ib.x + ic.x ia.y.next = ib.y + ic.y - return g_one, rtl + return one_inst, rtl + @block def c_testbench_one(): clock = Signal(bool(0)) - reset = ResetSignal(0,active=0,async=True) - ia = MyIntf() - ib = MyIntf() + reset = ResetSignal(0, active=0, async=True) + ia, ib = MyIntf(), MyIntf() - tb_dut = m_one_level(clock,reset,ia,ib) + tb_dut = one_level(clock, reset, ia, ib) @instance def tb_clk(): @@ -62,19 +61,19 @@ def c_testbench_one(): yield clock.posedge assert ia.x == 3 assert ia.y == 4 - print("%d %d %d %d"%(ia.x,ia.y,ib.x,ib.y)) + print("%d %d %d %d" % (ia.x, ia.y, ib.x, ib.y)) raise StopSimulation return tb_dut, tb_clk, tb_stim + @block def c_testbench_two(): clock = Signal(bool(0)) - reset = ResetSignal(0,active=0,async=True) - ia = MyIntf() - ib = MyIntf() + reset = ResetSignal(0, active=0, async=True) + ia, ib = MyIntf(), MyIntf() - tb_dut = m_two_level(clock,reset,ia,ib) + tb_dut = two_level(clock, reset, ia, ib) @instance def tb_clk(): @@ -94,36 +93,33 @@ def c_testbench_two(): yield clock.posedge assert ia.x == 5 assert ia.y == 7 - print("%d %d %d %d"%(ia.x,ia.y,ib.x,ib.y)) + print("%d %d %d %d" % (ia.x, ia.y, ib.x, ib.y)) raise StopSimulation return tb_dut, tb_clk, tb_stim + def test_one_level_analyze(): clock = Signal(bool(0)) - reset = ResetSignal(0,active=0,async=True) - ia = MyIntf() - ib = MyIntf() - analyze(m_one_level(clock,reset,ia,ib)) + reset = ResetSignal(0, active=0, async=True) + ia, ib = MyIntf(), MyIntf() + inst = one_level(clock, reset, ia, ib) + assert inst.analyze_convert() == 0 + def test_one_level_verify(): - assert verify(c_testbench_one()) == 0 + inst = c_testbench_one() + assert inst.verify_convert() == 0 + def test_two_level_analyze(): clock = Signal(bool(0)) - reset = ResetSignal(0,active=0,async=True) - ia = MyIntf() - ib = MyIntf() - analyze(m_two_level(clock,reset,ia,ib)) + reset = ResetSignal(0, active=0, async=True) + ia, ib = MyIntf(), MyIntf() + inst = two_level(clock, reset, ia, ib) + assert inst.analyze_convert() == 0 + def test_two_level_verify(): - assert verify(c_testbench_two()) == 0 - - -if __name__ == '__main__': - print(sys.argv[1]) - verify.simulator = analyze.simulator = sys.argv[1] - Simulation(c_testbench_one()).run() - Simulation(c_testbench_two()).run() - print(verify(c_testbench_one)) - print(verify(c_testbench_two)) + inst = c_testbench_two() + assert inst.verify_convert() == 0 diff --git a/myhdl/test/conversion/general/test_interfaces2.py b/myhdl/test/conversion/general/test_interfaces2.py index 48661061..2890e9ee 100644 --- a/myhdl/test/conversion/general/test_interfaces2.py +++ b/myhdl/test/conversion/general/test_interfaces2.py @@ -1,23 +1,21 @@ -from __future__ import absolute_import -import sys +from myhdl import (block, Signal, ResetSignal, intbv, always_seq, always_comb, + instance, delay, StopSimulation, ) -import myhdl -from myhdl import * -from myhdl.conversion import analyze,verify class Intf(object): def __init__(self): - self.x = Signal(intbv(1,min=-1111,max=1111)) - self.y = Signal(intbv(2,min=-2211,max=2211)) - self.z = Signal(intbv(3,min=-3311,max=3311)) + self.x = Signal(intbv(1, min=-1111, max=1111)) + self.y = Signal(intbv(2, min=-2211, max=2211)) + self.z = Signal(intbv(3, min=-3311, max=3311)) + @block -def m_modify(clock,reset,a): +def modify(clock, reset, a): intfa = Intf() - @always_seq(clock.posedge,reset=reset) + @always_seq(clock.posedge, reset=reset) def rtl_inc(): intfa.x.next = intfa.x + 1 intfa.y.next = intfa.y + 2 @@ -29,17 +27,18 @@ def m_modify(clock,reset,a): a.y.next = intfa.y + 2 a.z.next = intfa.z + 3 - return rtl_inc,rtl_add + return rtl_inc, rtl_add + @block -def m_test_intf(clock,reset,a,b,c): +def use_interfaces(clock, reset, a, b, c): intfa = Intf() intfaa = Intf() - gen_mod = m_modify(clock,reset,intfaa) + mod_inst = modify(clock, reset, intfaa) - @always_seq(clock.posedge,reset=reset) + @always_seq(clock.posedge, reset=reset) def rtl_inc(): intfa.x.next = intfa.x - 1 intfa.y.next = intfa.y - 2 @@ -59,12 +58,12 @@ def m_test_intf(clock,reset,a,b,c): a.y.next = intfaa.y + 2 a.z.next = intfaa.z + 3 - return gen_mod,rtl_inc,rtl_combine + return mod_inst, rtl_inc, rtl_combine @block def name_conflict_after_replace(clock, reset, a, a_x): - a_x_0 = [Signal(intbv(0)[len(a_x):]) for i in range(8)] + a_x_0 = [Signal(intbv(0)[len(a_x):]) for _ in range(8)] @always_seq(clock.posedge, reset=reset) def logic(): @@ -79,15 +78,17 @@ def test_name_conflict_after_replace(): reset = ResetSignal(0, active=0, async=False) a = Intf() a_x = Signal(intbv(0)[len(a.x):]) - assert conversion.analyze(name_conflict_after_replace(clock, reset, a, a_x)) == 0 + inst = name_conflict_after_replace(clock, reset, a, a_x) + assert inst.analyze_convert() == 0 + @block def c_testbench(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=False) - a,b,c = (Intf(),Intf(),Intf(),) + a, b, c = Intf(), Intf(), Intf() - tb_dut = m_test_intf(clock,reset,a,b,c) + tb_dut = use_interfaces(clock, reset, a, b, c) @instance def tb_clk(): @@ -104,25 +105,24 @@ def c_testbench(): reset.next = True yield delay(33) for ii in range(17): - print("a: x=%d y=%d z=%d"%(a.x,a.y,a.z)) - print("b: x=%d y=%d z=%d"%(b.x,b.y,b.z)) - print("c: x=%d y=%d z=%d"%(c.x,c.y,c.z)) + print("a: x=%d y=%d z=%d" % (a.x, a.y, a.z,)) + print("b: x=%d y=%d z=%d" % (b.x, b.y, b.z,)) + print("c: x=%d y=%d z=%d" % (c.x, c.y, c.z,)) yield clock.posedge raise StopSimulation - return tb_dut,tb_clk,tb_stim + return tb_dut, tb_clk, tb_stim + def test_name_conflicts_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=False) - a,b,c = (Intf(),Intf(),Intf(),) - analyze(m_test_intf(clock,reset,a,b,c)) + a, b, c = Intf(), Intf(), Intf() + inst = use_interfaces(clock, reset, a, b, c) + assert inst.analyze_convert() == 0 + def test_name_conflicts_verify(): - assert verify(c_testbench()) == 0 - -if __name__ == '__main__': - verify.simulator = analyze.simulator = sys.argv[1] - Simulation(c_testbench()).run() - print(verify(c_testbench)) + inst = c_testbench() + assert inst.verify_convert() == 0 diff --git a/myhdl/test/conversion/general/test_interfaces3.py b/myhdl/test/conversion/general/test_interfaces3.py index a9da68e6..b513ab40 100644 --- a/myhdl/test/conversion/general/test_interfaces3.py +++ b/myhdl/test/conversion/general/test_interfaces3.py @@ -2,30 +2,26 @@ from __future__ import absolute_import import sys -import pytest - import myhdl -from myhdl import * -from myhdl import ConversionError -from myhdl.conversion._misc import _error -from myhdl.conversion import analyze, verify - -import myhdl -from myhdl import * +from myhdl import (block, Signal, ResetSignal, intbv, always_comb, always_seq, + instance, delay, StopSimulation, ) class Intf1: def __init__(self, x): self.x = Signal(intbv(0, min=x.min, max=x.max)) + class Intf2: def __init__(self, y): self.y = Signal(intbv(0, min=y.min, max=y.max)) + class ZBus: def __init__(self, z): self.z = Signal(intbv(0, min=z.min, max=z.max)) + class Intf3: def __init__(self, z): self.z = ZBus(z) @@ -36,6 +32,7 @@ class IntfWithConstant1: self.const1 = 707 self.const2 = 3 + class IntfWithConstant2: def __init__(self): self.a = 9 @@ -45,50 +42,63 @@ class IntfWithConstant2: @block -def m_assign(y, x): +def assign(y, x): @always_comb - def assign(): + def beh_assign(): y.next = x - return assign + return beh_assign + @block -def m_top_assign(x,y,z): - """ - This module does not test top-level interfaces, - it only tests intermediate interfaces. - """ - i1,i2 = Intf1(x), Intf2(y) - - ga1 = m_assign(x, i1.x) # x = i1.x - ga2 = m_assign(i2.y, y) # i2.y = y - gm1 = m_assign_intf(i1, i2) - - return ga1, ga2, gm1 - -@block -def m_assign_intf(x, y): +def assign_intf(x, y): @always_comb def rtl(): x.x.next = y.y return rtl + +@block +def top_assign(x, y, z): + """ + This module does not test top-level interfaces, + it only tests intermediate interfaces. + """ + i1, i2 = Intf1(x), Intf2(y) + + inst1 = assign(x, i1.x) # x = i1.x + inst2 = assign(i2.y, y) # i2.y = y + inst3 = assign_intf(i1, i2) + + return myhdl.instances() + + @block def c_testbench_one(): - x,y,z = [Signal(intbv(0, min=-8, max=8)) - for _ in range(3)] + x, y, z = [Signal(intbv(0, min=-8, max=8)) + for _ in range(3)] + + tb_dut = top_assign(x, y, z) - tb_dut = m_top_assign(x,y,z) @instance def tb_stim(): y.next = 3 yield delay(10) - print("x: %d" % (x)) + print("x: %d" % (x,)) assert x == 3 return tb_dut, tb_stim - + + @block -def m_top_multi_comb(x,y,z): +def multi_comb(x, y, z): + @always_comb + def rtl(): + x.x.next = y.y + z.z.z + return rtl + + +@block +def top_multi_comb(x, y, z): """ This module does not test top-level interfaces, it only tests intermediate interfaces. @@ -97,34 +107,29 @@ def m_top_multi_comb(x,y,z): x.assign(intf[0].x) intf[1].y.assign(y) intf[2].z.z.assign(z) - gm = m_multi_comb(*intf) - return gm + inst = multi_comb(*intf) + return inst -@block -def m_multi_comb(x, y, z): - @always_comb - def rtl(): - x.x.next = y.y + z.z.z - return rtl @block def c_testbench_two(): - x,y,z = [Signal(intbv(0, min=-8, max=8)) - for _ in range(3)] - tb_dut = m_top_multi_comb(x,y,z) + x, y, z = [Signal(intbv(0, min=-8, max=8)) + for _ in range(3)] + tb_dut = top_multi_comb(x, y, z) + @instance def tb_stim(): y.next = 3 z.next = 2 yield delay(10) - print("x: %d" % (x)) + print("x: %d" % (x,)) assert x == 5 return tb_dut, tb_stim @block -def m_top_const(clock, reset, x, y, intf): +def top_const(clock, reset, x, y, intf): @always_seq(clock.posedge, reset=reset) def rtl1(): @@ -138,6 +143,7 @@ def m_top_const(clock, reset, x, y, intf): return rtl1, rtl2 + @block def c_testbench_three(): """ @@ -150,7 +156,7 @@ def c_testbench_three(): y = Signal(intbv(4, min=-200, max=200)) intf = IntfWithConstant2() - tbdut = m_top_const(clock, reset, x, y, intf) + tbdut = top_const(clock, reset, x, y, intf) @instance def tbclk(): @@ -174,31 +180,40 @@ def c_testbench_three(): return tbdut, tbclk, tbstim + def test_one_analyze(): - x,y,z = [Signal(intbv(0, min=-8, max=8)) - for _ in range(3)] + x, y, z = [Signal(intbv(0, min=-8, max=8)) + for _ in range(3)] # fool name check in convertor # to be reviewed x._name = 'x' y._name = 'y' z._name = 'z' - analyze(m_top_assign(x, y, z)) + inst = top_assign(x, y, z) + assert inst.analyze_convert() == 0 + def test_one_verify(): - assert verify(c_testbench_one()) == 0 + inst = c_testbench_one() + assert inst.verify_convert() == 0 + def test_two_analyze(): - x,y,z = [Signal(intbv(0, min=-8, max=8)) - for _ in range(3)] - # fool name check in convertor + x, y, z = [Signal(intbv(0, min=-8, max=8)) + for _ in range(3)] + # fool name check in converter # to be reviewed x._name = 'x' y._name = 'y' z._name = 'z' - analyze(m_top_multi_comb(x, y, z)) + inst = top_multi_comb(x, y, z) + assert inst.analyze_convert() == 0 + def test_two_verify(): - assert verify(c_testbench_two()) == 0 + inst = c_testbench_two() + assert inst.verify_convert() == 0 + def test_three_analyze(): clock = Signal(bool(0)) @@ -206,25 +221,10 @@ def test_three_analyze(): x = Signal(intbv(3, min=-5000, max=5000)) y = Signal(intbv(4, min=-200, max=200)) intf = IntfWithConstant2() - analyze(m_top_const(clock, reset, x, y, intf)) + inst = top_const(clock, reset, x, y, intf) + assert inst.analyze_convert() == 0 + def test_three_verify(): - assert verify(c_testbench_three()) == 0 - - -if __name__ == '__main__': - print(sys.argv[1]) - verify.simulator = analyze.simulator = sys.argv[1] - print("*** verify myhdl simulation") - Simulation(c_testbench_one()).run() - Simulation(c_testbench_two()).run() - Simulation(c_testbench_three()).run() - print("*** myhdl simulation ok") - print("") - - print("*** myhdl verify conversion") - print(verify(c_testbench_one)) - print(verify(c_testbench_two)) - print(verify(c_testbench_three)) - print("*** myhdl conversion ok") - print("") + inst = c_testbench_three() + assert inst.verify_convert() == 0