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_toVerilog.py: 'skip_zero_mem_init': repaired test for 'zero' value :( (#433)

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* _toVerilog.py: 'skip_zero_mem_init': repaired test for 'zero' value :(

* incremented subminor version number
This commit is contained in:
Josy Boelen 2024-06-14 08:39:27 +02:00 committed by GitHub
parent ac9b87c273
commit e3b4d5263a
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2 changed files with 2 additions and 2 deletions
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2
myhdl/__init__.py
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@ -49,7 +49,7 @@ traceSignals -- function that enables signal tracing in a VCD file
toVerilog -- function that converts a design to Verilog
"""
__version__ = "0.11.48"
__version__ = "0.11.49"
class StopSimulation(Exception):

2
myhdl/conversion/_toVerilog.py
View File

@ -381,7 +381,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
if toVerilog.initial_values and not k == 'wire':
if all([each._init == m.mem[0]._init for each in m.mem]):
if toVerilog.initial_values == 'skip_zero_mem_init' and _intRepr(m.mem[0]._init) == 0:
if toVerilog.initial_values == 'skip_zero_mem_init' and int(m.mem[0]._init) == 0:
pass
else:
initialize_block_name = ('INITIALIZE_' + m.name).upper()