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Rename BlockInstance to Block

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This commit is contained in:
Jan Decaluwe 2016-03-19 17:28:55 +01:00
parent a12b67f040
commit e4550bc5a7
8 changed files with 30 additions and 38 deletions
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4
myhdl/_Simulation.py
View File

@ -34,7 +34,7 @@ from myhdl._simulator import _signals, _siglist, _futureEvents
from myhdl._Waiter import _Waiter, _inferWaiter, _SignalWaiter,_SignalTupleWaiter
from myhdl._util import _printExcInfo
from myhdl._instance import _Instantiator
from myhdl._block import _BlockInstance
from myhdl._block import _Block
from myhdl._ShadowSignal import _ShadowSignal
schedule = _futureEvents.append
@ -49,7 +49,7 @@ _error.DuplicatedArg = "Duplicated argument"
def _flatten(*args):
arglist = []
for arg in args:
if isinstance(arg, _BlockInstance):
if isinstance(arg, _Block):
arg = arg.subs
if isinstance(arg, (list, tuple, set)):
for item in arg:

11
myhdl/_block.py
View File

@ -73,7 +73,7 @@ def _getCallInfo():
if callerrec is not None:
f_locals = callerrec[0].f_locals
if 'self' in f_locals:
modctxt = isinstance(f_locals['self'], _BlockInstance)
modctxt = isinstance(f_locals['self'], _Block)
return _CallInfo(name, modctxt, symdict)
def block(func):
@ -82,12 +82,11 @@ def block(func):
@wraps(func)
def deco(*args, **kwargs):
deco.calls += 1
return _BlockInstance(func, deco, srcfile, srcline,
*args, **kwargs)
return _Block(func, deco, srcfile, srcline, *args, **kwargs)
deco.calls = 0
return deco
class _BlockInstance(object):
class _Block(object):
def __init__(self, func, deco, srcfile, srcline, *args, **kwargs):
calls = deco.calls
@ -119,9 +118,9 @@ class _BlockInstance(object):
def _verifySubs(self):
for inst in self.subs:
if not isinstance(inst, (_BlockInstance, _Instantiator, Cosimulation)):
if not isinstance(inst, (_Block, _Instantiator, Cosimulation)):
raise BlockError(_error.ArgType)
if isinstance(inst, (_BlockInstance, _Instantiator)):
if isinstance(inst, (_Block, _Instantiator)):
if not inst.modctxt:
raise BlockError(_error.InstanceError % (self.mod.name, inst.callername))

4
myhdl/_getHierarchy.py
View File

@ -25,7 +25,7 @@ from __future__ import absolute_import
from myhdl._extractHierarchy import _Instance
from myhdl._instance import _Instantiator
from myhdl._block import _BlockInstance
from myhdl._block import _Block
class _Hierarchy(object):
def __init__(self, name, modinst):
@ -59,5 +59,5 @@ def _getHierarchyHelper(level, modinst, hierarchy):
inst = _Instance(level, modinst, subs, modinst.sigdict, modinst.memdict)
hierarchy.append(inst)
for inst in modinst.subs:
if isinstance(inst, _BlockInstance):
if isinstance(inst, _Block):
_getHierarchyHelper(level+1, inst, hierarchy)

2
myhdl/_instance.py
View File

@ -63,7 +63,7 @@ def _getCallInfo():
callerrec = inspect.stack()[3]
f_locals = callerrec[0].f_locals
if 'self' in f_locals:
modctxt = isinstance(f_locals['self'], _block._BlockInstance)
modctxt = isinstance(f_locals['self'], _block._Block)
return _CallInfo(name, modctxt, symdict)

13
myhdl/_traceSignals.py
View File

@ -36,7 +36,7 @@ from myhdl import _simulator, __version__, EnumItemType
from myhdl._extractHierarchy import _HierExtr
from myhdl import TraceSignalsError
from myhdl._ShadowSignal import _TristateSignal, _TristateDriver
from myhdl._block import _BlockInstance
from myhdl._block import _Block
from myhdl._getHierarchy import _getHierarchy
_tracing = 0
@ -68,7 +68,7 @@ class _TraceSignalsClass(object):
def __call__(self, dut, *args, **kwargs):
global _tracing, vcdpath
if isinstance(dut, _BlockInstance):
if isinstance(dut, _Block):
# now we go bottom-up: so clean up and start over
# TODO: consider a warning for the overruled block
if _simulator._tracing:
@ -85,7 +85,7 @@ class _TraceSignalsClass(object):
from myhdl.conversion import _toVerilog
if _toVerilog._converting:
raise TraceSignalsError("Cannot use traceSignals while converting to Verilog")
if not isinstance(dut, _BlockInstance):
if not isinstance(dut, _Block):
if not callable(dut):
raise TraceSignalsError(_error.ArgType, "got %s" % type(dut))
if _simulator._tracing:
@ -95,7 +95,7 @@ class _TraceSignalsClass(object):
try:
if self.name is None:
name = dut.__name__
if isinstance(dut, _BlockInstance):
if isinstance(dut, _Block):
name = dut.func.__name__
else:
name = str(self.name)
@ -107,10 +107,7 @@ class _TraceSignalsClass(object):
else:
directory = self.directory
#if isinstance(dut, _Block):
# raise TypeError("Block %s: conversion should be on an instance" % dut.__name__)
if isinstance(dut, _BlockInstance):
if isinstance(dut, _Block):
h = _getHierarchy(name, dut)
else:
warnings.warn("\n traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2)

12
myhdl/conversion/_toVHDL.py
View File

@ -56,7 +56,7 @@ from myhdl._util import _flatten
from myhdl._compat import integer_types, class_types, StringIO
from myhdl._ShadowSignal import _TristateSignal, _TristateDriver
from myhdl._block import _BlockInstance
from myhdl._block import _Block
from myhdl._getHierarchy import _getHierarchy
_version = myhdl.__version__.replace('.','')
@ -73,7 +73,7 @@ def _checkArgs(arglist):
def _flatten(*args):
arglist = []
for arg in args:
if isinstance(arg, _BlockInstance):
if isinstance(arg, _Block):
if arg.vhdl_code is not None:
arglist.append(arg.vhdl_code)
continue
@ -134,19 +134,19 @@ class _ToVHDLConvertor(object):
from myhdl import _traceSignals
if _traceSignals._tracing:
raise ToVHDLError("Cannot use toVHDL while tracing signals")
if not isinstance(func, _BlockInstance):
if not isinstance(func, _Block):
if not callable(func):
raise ToVHDLError(_error.FirstArgType, "got %s" % type(func))
_converting = 1
if self.name is None:
name = func.__name__
if isinstance(func, _BlockInstance):
if isinstance(func, _Block):
name = func.func.__name__
else:
name = str(self.name)
if isinstance(func, _BlockInstance):
if isinstance(func, _Block):
try:
h = _getHierarchy(name, func)
finally:
@ -190,7 +190,7 @@ class _ToVHDLConvertor(object):
_annotateTypes(genlist)
### infer interface
if isinstance(func, _BlockInstance):
if isinstance(func, _Block):
# infer interface after signals have been analyzed
func._inferInterface()
intf = func

14
myhdl/conversion/_toVerilog.py
View File

@ -53,7 +53,7 @@ from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFu
from myhdl._Signal import _Signal
from myhdl._ShadowSignal import _TristateSignal, _TristateDriver
from myhdl._block import _BlockInstance
from myhdl._block import _Block
from myhdl._getHierarchy import _getHierarchy
_converting = 0
@ -67,7 +67,7 @@ def _checkArgs(arglist):
def _flatten(*args):
arglist = []
for arg in args:
if isinstance(arg, _BlockInstance):
if isinstance(arg, _Block):
if arg.verilog_code is not None:
arglist.append(arg.verilog_code)
continue
@ -130,27 +130,25 @@ class _ToVerilogConvertor(object):
from myhdl import _traceSignals
if _traceSignals._tracing:
raise ToVerilogError("Cannot use toVerilog while tracing signals")
if not isinstance(func, _BlockInstance):
if not isinstance(func, _Block):
if not callable(func):
raise ToVerilogError(_error.FirstArgType, "got %s" % type(func))
_converting = 1
if self.name is None:
name = func.__name__
if isinstance(func, _BlockInstance):
if isinstance(func, _Block):
name = func.func.__name__
else:
name = str(self.name)
if isinstance(func, _BlockInstance):
if isinstance(func, _Block):
try:
h = _getHierarchy(name, func)
finally:
_converting = 0
else:
warnings.warn("\n toVerilog(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2)
#if isinstance(func, _Block):
# raise TypeError("Block %s: conversion should be on an instance" % func.__name__)
try:
h = _HierExtr(name, func, *args, **kwargs)
finally:
@ -176,7 +174,7 @@ class _ToVerilogConvertor(object):
_annotateTypes(genlist)
### infer interface
if isinstance(func, _BlockInstance):
if isinstance(func, _Block):
# infer interface after signals have been analyzed
func._inferInterface()
intf = func

8
myhdl/conversion/_verify.py
View File

@ -13,7 +13,7 @@ import myhdl
from myhdl._Simulation import Simulation
from myhdl.conversion._toVHDL import toVHDL
from myhdl.conversion._toVerilog import toVerilog
from myhdl._block import _BlockInstance
from myhdl._block import _Block
_version = myhdl.__version__.replace('.','')
# strip 'dev' for version
@ -114,7 +114,7 @@ class _VerificationClass(object):
name = toVerilog.name
elif hdl == 'VHDL' and toVHDL.name is not None:
name = toVHDL.name
elif isinstance(func, _BlockInstance):
elif isinstance(func, _Block):
name = func.func.__name__
else:
warnings.warn("\n analyze()/verify(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2)
@ -137,14 +137,12 @@ class _VerificationClass(object):
skipchars = hdlsim.skipchars
ignore = hdlsim.ignore
if isinstance(func, _BlockInstance):
if isinstance(func, _Block):
if hdl == "VHDL":
inst = func.convert(hdl='VHDL')
else:
inst = func.convert(hdl='Verilog')
else:
#if isinstance(func, _Block):
# raise TypeError("Block %s: conversion should be on an instance" % func.__name__)
if hdl == "VHDL":
inst = toVHDL(func, *args, **kwargs)
else: