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jand 2006-10-04 15:28:04 +00:00
parent 81ee5b2159
commit e5d346b79d
2 changed files with 2 additions and 2 deletions
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2
MANIFEST.in
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@ -8,7 +8,7 @@ global-include makefile*
global-include *.v
prune dist
prune doc
graft doc/html/manual
#graft doc/html/manual
#graft doc/html/icons
#graft doc/html/whatsnew*
#include doc/paper-a4/MyHDL.pdf

2
setup.py
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@ -39,7 +39,7 @@ setup(name="myhdl",
author_email="jan@jandecaluwe.com",
url="http://jandecaluwe.com/Tools/MyHDL/Overview.html",
download_url="http://sourceforge.net/project/showfiles.php?group_id=91207",
packages=['myhdl', 'myhdl._toVerilog'],
packages=['myhdl', 'myhdl.conversion'],
license="LGPL",
platforms=["Any"],
keywords="HDL ASIC FPGA hardware design",