From e6579efa7364178da2f627839667e81b64c23ece Mon Sep 17 00:00:00 2001 From: jand Date: Thu, 29 Dec 2005 21:20:02 +0000 Subject: [PATCH] proofread --- doc/manual/cosimulation.tex | 4 ++-- doc/manual/modeling.tex | 7 +++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/doc/manual/cosimulation.tex b/doc/manual/cosimulation.tex index 2010806b..ca016c71 100644 --- a/doc/manual/cosimulation.tex +++ b/doc/manual/cosimulation.tex @@ -22,8 +22,8 @@ has a procedural language interface (PLI). The \myhdl\ side is designed to be independent of a particular simulator, On the other hand, for each HDL simulator a specific PLI module will have to be written in C. Currently, -the \myhdl\ release contains a PLI module to interface -with the Icarus and Cver Verilog simulators. +the \myhdl\ release contains a PLI module for +two Verilog simulators: Icarus and Cver. \section{The HDL side \label{cosim-hdl}} diff --git a/doc/manual/modeling.tex b/doc/manual/modeling.tex index 45131aaa..4a9c5ba7 100644 --- a/doc/manual/modeling.tex +++ b/doc/manual/modeling.tex @@ -133,7 +133,7 @@ Combinatorial logic is described with a code pattern as follows: \begin{verbatim} -def top() +def top(): ... @always_comb def combLogic(): @@ -238,7 +238,7 @@ common patterns: a template with a rising clock edge and an asynchronous reset signal. Other templates are similar. \begin{verbatim} -def top(, clock, ..., reset, ...) +def top(, clock, ..., reset, ...): ... @always(clock.posedge, reset.negedge) def seqLogic(): @@ -487,8 +487,7 @@ instead: tb_fsm = traceSignals(testbench) \end{verbatim} -All signals in the instance hierarchy will be traced in an output VCD -file called \file{tb_fsm.vcd}. Note that first the argument of +Note that the first argument of \function{traceSignals()} consists of the uncalled function. By calling the function under its control, \function{traceSignals()} gathers information about the hierarchy and the signals to be traced.