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improve assert conversion to Verilog

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make sure x-values trigger assertions
This commit is contained in:
jand 2008-01-07 20:37:24 +00:00
parent a45c9d4c82
commit e6b9c54c3d
1 changed files with 5 additions and 4 deletions
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9
myhdl/conversion/_toVerilog.py
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@ -222,6 +222,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
print >> f
for s in constwires:
print >> f, "assign %s = %s;" % (s._name, int(s._val))
print >> f
def _writeModuleFooter(f):
@ -460,14 +461,14 @@ class _ConvertVisitor(_ConversionMixin):
self.visit(node.expr)
def visitAssert(self, node, *args):
self.write("if (!")
self.write("if (")
self.visit(node.test)
self.write(") begin")
self.write(" !== 1) begin")
self.indent()
self.writeline()
self.write('$display("AssertionError");')
self.writeline()
self.write('$finish;')
# self.writeline()
# self.write('$finish;')
self.dedent()
self.writeline()
self.write("end")