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UNSTABLE - replace compiler by ast for conversion
Tests in conversion/general for Verilog work.
This commit is contained in:
Jan Decaluwe
parent
c962b8542e
commit
e6ba8d4ec1
@ -139,7 +139,6 @@ def _analyzeGens(top, absnames):
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s = inspect.getsource(f)
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s = _dedent(s)
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tree = ast.parse(s)
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#print ast.dump(tree)
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tree.sourcefile = inspect.getsourcefile(f)
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tree.lineoffset = inspect.getsourcelines(f)[1]-1
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tree.symdict = f.func_globals.copy()
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@ -166,7 +165,6 @@ def _analyzeGens(top, absnames):
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s = inspect.getsource(f)
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s = _dedent(s)
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tree = ast.parse(s)
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# print ast.dump(tree)
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tree.sourcefile = inspect.getsourcefile(f)
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tree.lineoffset = inspect.getsourcelines(f)[1]-1
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tree.symdict = f.f_globals.copy()
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@ -279,7 +277,8 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
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self.raiseError(node, _error.NotSupported, "embedded function definition")
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self.toplevel = False
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node.argnames = [arg.id for arg in node.args.args]
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self.generic_visit(node)
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# don't visit decorator lists - they can support more than other calls
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self.visitList(node.body)
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def flattenIf(self, node, tests):
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""" Flatten if-then-else as in compiler package."""
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@ -485,7 +484,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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node.signed = node.operand.signed
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if isinstance(op, ast.Not):
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node.obj = bool()
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elif isintance(op, ast.UAdd):
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elif isinstance(op, ast.UAdd):
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node.obj = int(-1)
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elif isinstance(op, ast.USub):
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node.obj = int(-1)
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@ -545,16 +544,16 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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if node.attr != 'next':
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self.raiseError(node, _error.NotSupported, "attribute assignment")
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self.tree.kind = _kind.TASK
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self.access = _access.OUTPUT
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# self.access = _access.OUTPUT
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self.visit(node.value)
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self.access = _access.INPUT
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# self.access = _access.INPUT
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def getAttr(self, node):
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self.visit(node.value)
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node.obj = None
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node.signed = False
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if isinstance(node.value, astNode.Name):
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n = node.value.name
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if isinstance(node.value, ast.Name):
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n = node.value.id
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if (n not in self.tree.vardict) and (n not in self.tree.symdict):
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raise AssertionError("attribute target: %s" % n)
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obj = node.value.obj
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@ -869,11 +868,12 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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def visit_Compare(self, node):
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node.obj = bool()
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node.signed = False
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for n in ast.iter_field_nodes(node):
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#for n in ast.iter_child_nodes(node):
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for n in [node.left] + node.comparators:
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self.visit(n)
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if n.signed:
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node.signed = True
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op, arg = ops[0], compartors[0]
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op, arg = node.ops[0], node.comparators[0]
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## node.expr.target = self.getObj(arg)
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## arg.target = self.getObj(node.expr)
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# detect specialized case for the test
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@ -1029,11 +1029,11 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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for test, suite in node.tests:
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self.visit(test)
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self.refStack.push()
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self.visit(suite)
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self.visitList(suite)
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self.refStack.pop()
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if node.else_:
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self.refStack.push()
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self.visit(node.else_)
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self.visitList(node.else_)
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self.refStack.pop()
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# check whether the if can be mapped to a (parallel) case
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node.isCase = node.isFullCase = False
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@ -1164,14 +1164,28 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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self.getName(node)
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def setName(self, node):
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# XXX INOUT access in Store context, unlike with compiler
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# XXX check whether ast context is correct
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n = node.id
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if n in ("__verilog__", "__vhdl__"):
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self.raiseError(node, _error.NotSupported,
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"%s in generator function" % n)
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# XXX ?
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if n in self.globalRefs:
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self.raiseError(node, _error.UnboundLocal, n)
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self.refStack.add(n)
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if self.access == _access.INOUT: # augmented assign
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if n in self.tree.sigdict:
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sig = self.tree.sigdict[n]
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if isinstance(sig, Signal):
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self.raiseError(node, _error.NotSupported, "Augmented signal assignment")
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if n in self.tree.vardict:
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obj = self.tree.vardict[n]
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# upgrade bool to int for augmented assignments
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if isinstance(obj, bool):
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obj = int(0)
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self.tree.vardict[n] = obj
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node.obj = obj
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else:
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if n in ("__verilog__", "__vhdl__"):
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self.raiseError(node, _error.NotSupported,
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"%s in generator function" % n)
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if n in self.globalRefs:
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self.raiseError(node, _error.UnboundLocal, n)
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self.refStack.add(n)
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def getName(self, node):
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n = node.id
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@ -1201,7 +1215,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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self.raiseError(node, _error.NotSupported, "Augmented signal assignment")
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if n in self.tree.vardict:
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obj = self.tree.vardict[n]
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if self.access == _access.INOUT:
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if self.access == _access.INOUT: # probably dead code
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# upgrade bool to int for augmented assignments
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if isinstance(obj, bool):
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obj = int(0)
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@ -1302,7 +1316,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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a.extend(n.right.elts)
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else:
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a.append(n.right)
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s = n.left.value
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s = n.left.s
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while s:
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if not s:
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break
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@ -1417,7 +1431,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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self.access = _access.INPUT
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self.visit(node.slice.value)
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if isinstance(node.value.obj, _Ram):
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if node.flags == 'OP_ASSIGN':
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if isinstance(node.ctx, ast.Store):
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self.raiseError(node, _error.ListElementAssign)
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else:
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node.obj = node.value.obj.elObj
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@ -333,6 +333,12 @@ opmap = {
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ast.Not : '!',
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ast.UAdd : '+',
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ast.USub : '-',
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ast.Eq : '==',
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ast.Gt : '>',
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ast.GtE : '>=',
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ast.Lt : '<',
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ast.LtE : '<=',
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ast.NotEq : '!=',
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}
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@ -528,7 +534,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.write("(")
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self.visit(node.values[0])
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for n in node.nodes[1:]:
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self.write(" %s " % opmap[node.op])
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self.write(" %s " % opmap[type(node.op)])
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self.visit(n)
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self.write(")")
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@ -551,7 +557,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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def visit_UnaryOp(self, node):
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self.write("(%s" % opmap[node.op])
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self.write("(%s" % opmap[type(node.op)])
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self.visit(node.operand)
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self.write(")")
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@ -562,12 +568,71 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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# self.isSigAss = True
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# self.visit(node.expr)
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# def visitGetattr(self, node, *args):
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# assert isinstance(node.expr, astNode.Name)
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# n = node.expr.name
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# if n in self.tree.symdict:
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# obj = self.tree.symdict[n]
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# elif n in self.tree.vardict:
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# obj = self.tree.vardict[n]
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# else:
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# raise AssertionError("object not found")
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# if isinstance(obj, Signal):
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# if node.attrname == 'next':
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# self.isSigAss = True
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# self.visit(node.expr)
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# elif node.attrname in ('posedge', 'negedge'):
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# self.write(node.attrname)
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# self.write(' ')
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# self.visit(node.expr)
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# elif node.attrname == 'val':
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# self.visit(node.expr)
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# if isinstance(obj, (Signal, intbv)):
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# if node.attrname in ('min', 'max'):
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# self.write("%s" % node.obj)
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# if isinstance(obj, EnumType):
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# assert hasattr(obj, node.attrname)
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# e = getattr(obj, node.attrname)
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# self.write(e._toVerilog())
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def visit_Attribute(self, node):
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if isinstance(node.ctx, ast.Store):
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assert node.attr == 'next'
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self.isSigAss = True
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self.visit(node.value)
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self.setAttr(node)
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else:
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self.getAttr(node)
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def setAttr(self, node):
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assert node.attr == 'next'
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self.isSigAss = True
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self.visit(node.value)
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def getAttr(self, node):
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assert isinstance(node.value, ast.Name)
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n = node.value.id
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if n in self.tree.symdict:
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obj = self.tree.symdict[n]
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elif n in self.tree.vardict:
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obj = self.tree.vardict[n]
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else:
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raise AssertionError("object not found")
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if isinstance(obj, Signal):
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if node.attr == 'next':
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self.isSigAss = True
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self.visit(node.value)
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elif node.attr in ('posedge', 'negedge'):
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self.write(node.attr)
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self.write(' ')
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self.visit(node.value)
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elif node.attr == 'val':
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self.visit(node.value)
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if isinstance(obj, (Signal, intbv)):
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if node.attr in ('min', 'max'):
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self.write("%s" % node.obj)
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if isinstance(obj, EnumType):
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assert hasattr(obj, node.attr)
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e = getattr(obj, node.attr)
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self.write(e._toVerilog())
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# def visitAssert(self, node, *args):
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@ -803,6 +868,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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def visit_Call(self, node):
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self.context = None
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fn = node.func
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# assert isinstance(fn, astNode.Name)
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f = self.getObj(fn)
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@ -839,10 +905,10 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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elif f == intbv.signed: # note equality comparison
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# comes from a getattr
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opening, closing = '', ''
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if not fn.expr.signed:
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if not fn.value.signed:
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opening, closing = "$signed(", ")"
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self.write(opening)
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self.visit(fn.expr)
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self.visit(fn.value)
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self.write(closing)
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elif type(f) in (ClassType, TypeType) and issubclass(f, Exception):
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self.write(f.__name__)
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@ -874,16 +940,27 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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v.visit(node.tree)
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def visitCompare(self, node, *args):
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context = None
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# def visitCompare(self, node, *args):
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# context = None
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# if node.signed:
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# context = _context.SIGNED
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# self.write("(")
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# self.visit(node.expr, context)
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# op, code = node.ops[0]
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# self.write(" %s " % op)
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# self.visit(code, context)
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# self.write(")")
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def visit_Compare(self, node):
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self.context = None
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if node.signed:
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context = _context.SIGNED
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self.context = _context.SIGNED
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self.write("(")
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self.visit(node.expr, context)
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op, code = node.ops[0]
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self.write(" %s " % op)
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self.visit(code, context)
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self.visit(node.left)
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self.write(" %s " % opmap[type(node.ops[0])])
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self.visit(node.comparators[0])
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self.write(")")
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self.context = None
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@ -1072,33 +1149,6 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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def visitGetattr(self, node, *args):
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assert isinstance(node.expr, astNode.Name)
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n = node.expr.name
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if n in self.tree.symdict:
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obj = self.tree.symdict[n]
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elif n in self.tree.vardict:
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obj = self.tree.vardict[n]
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else:
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raise AssertionError("object not found")
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if isinstance(obj, Signal):
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if node.attrname == 'next':
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self.isSigAss = True
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self.visit(node.expr)
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elif node.attrname in ('posedge', 'negedge'):
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self.write(node.attrname)
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self.write(' ')
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self.visit(node.expr)
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elif node.attrname == 'val':
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self.visit(node.expr)
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if isinstance(obj, (Signal, intbv)):
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if node.attrname in ('min', 'max'):
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self.write("%s" % node.obj)
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if isinstance(obj, EnumType):
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assert hasattr(obj, node.attrname)
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e = getattr(obj, node.attrname)
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self.write(e._toVerilog())
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# def visitIf(self, node, *args):
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@ -1133,7 +1183,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.write(item._toVerilog(dontcare=True))
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self.write(": begin")
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self.indent()
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self.visit(suite)
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self.visit_stmt(suite)
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self.dedent()
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self.writeline()
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self.write("end")
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@ -1141,7 +1191,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.writeline()
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self.write("default: begin")
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self.indent()
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self.visit(node.else_)
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self.visit_stmt(node.else_)
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self.dedent()
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self.writeline()
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self.write("end")
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@ -1162,7 +1212,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.visit(test)
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self.write(") begin")
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self.indent()
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self.visit(suite)
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self.visit_stmt(suite)
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self.dedent()
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self.writeline()
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self.write("end")
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@ -1170,7 +1220,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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self.writeline()
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self.write("else begin")
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self.indent()
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self.visit(node.else_)
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self.visit_stmt(node.else_)
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self.dedent()
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self.writeline()
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self.write("end")
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@ -1364,7 +1414,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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if isinstance(s, str):
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self.write('$write("%s");' % s)
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else:
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a = node.values[argnr]
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a = node.args[argnr]
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argnr += 1
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obj = a.obj
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fs = "%0d"
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@ -1549,7 +1599,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
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# self.visit(elt)
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def visitTuple(self, node):
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def visit_Tuple(self, node):
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assert self.context != None
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sep = ", "
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tpl = node.elts
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@ -1747,7 +1797,7 @@ class _ConvertSimpleAlwaysCombVisitor(_ConvertVisitor):
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# self.visit(node.expr)
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def visit_Attribute(self, node):
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if isintance(node.ctx, ast.Store):
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if isinstance(node.ctx, ast.Store):
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self.write("assign ")
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self.visit(node.value)
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else:
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@ -1758,8 +1808,7 @@ class _ConvertSimpleAlwaysCombVisitor(_ConvertVisitor):
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# self.writeline(2)
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def visit_FunctionDef(self, node):
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for stmt in node.body:
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self.visit(node.body)
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self.visit_stmt(node.body)
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self.writeline(2)
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