Fix for bug 42

myhdl/_always_comb.py

@@ -126,6 +126,16 @@ class _SigNameVisitor(ast.NodeVisitor):
     def visit_Attribute(self, node):
         self.visit(node.value)
 
+    def visit_Call(self, node):
+        fn = None
+        if isinstance(node.func, ast.Name):
+            fn = node.func.id
+        if fn == "len":
+            pass
+        else:
+            self.generic_visit(node)
+            
+
     def visit_Subscript(self, node, access=INPUT):
         self.visit(node.value)
         self.context = INPUT

myhdl/conversion/_analyze.py

@@ -578,6 +578,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
         elif f is concat:
             node.obj = self.getVal(node)
         elif f is len:
+            self.access = _access.UNKNOWN
             node.obj = int(0) # XXX
         elif f is bool:
             node.obj = bool()

myhdl/test/bugs/test_bug_42.py

@@ -0,0 +1,22 @@
+#! /usr/bin/env python
+
+from myhdl import *
+
+def module(sigin, sigout):
+
+    # Using @always(sigin) only warns, but using @always_comp breaks.
+    # The reason is that len(sigout) is interpreted as sigout being used as
+    # an input.
+    #@always(sigin)
+    @always_comb
+    def output():
+         sigout.next = sigin[len(sigout):]
+
+    return output
+
+sigin = Signal(intbv(0)[2:])
+sigout = Signal(intbv(0)[2:])
+
+def test_bug_42():
+    toVHDL(module, sigin, sigout)
+

myhdl/test/bugs/test_bug_42_2.py

@@ -0,0 +1,24 @@
+#! /usr/bin/env python
+
+from myhdl import *
+
+def module(sigin, sigout):
+
+    # Using @always(sigin) only warns, but using @always_comp breaks.
+    # The reason is that len(sigout) is interpreted as sigout being used as
+    # an input.
+    @always(sigin)
+    def output():
+         sigout.next = sigin[len(sigout):]
+
+    return output
+
+sigin = Signal(intbv(0)[2:])
+sigout = Signal(intbv(0)[2:])
+
+def test_bug_42_2():
+    toVHDL(module, sigin, sigout)
+
+toVHDL(module, sigin, sigout)
+
+