Updated jck's pull request up to 70f83a

--HG--
branch : 0.9-dev

myhdl/conversion/_analyze.py

@@ -53,7 +53,16 @@ _constDict = {}
 _extConstDict = {}
 
 
-def _makeName(n, prefixes):
+def _makeName(n, prefixes, namedict):
+    #Take care of names with periods
+    #For attribute references, periods are replaced with '_'.
+    if '.' in n:
+        n = n.replace('.', '_')
+        if n in namedict:
+            i = 0
+            while (n + '_{}'.format(i)) in namedict:
+                i += 1
+            n += '_{}'.format(i)
     # trim empty prefixes
     prefixes = [p for p in prefixes if p]
     if len(prefixes) > 1:
@@ -90,6 +99,7 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
         name = inst.name
         sigdict = inst.sigdict
         memdict = inst.memdict
+        namedict = dict(sigdict.items() + memdict.items())
         delta = curlevel - level
         curlevel = level
         assert(delta >= -1)
@@ -103,13 +113,9 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
         for n, s in sigdict.items():
             if s._name is not None:
                 continue
-            if '.' in n:
-                n = n.replace('.', '_')
-                while n in sigdict:
-                    n = n + '_'
             if isinstance(s, _SliceSignal):
                 continue
-            s._name = _makeName(n, prefixes)
+            s._name = _makeName(n, prefixes, namedict)
             if not s._nrbits:
                 raise ConversionError(_error.UndefinedBitWidth, s._name)
             # slice signals
@@ -120,7 +126,7 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
         for n, m in memdict.items():
             if m.name is not None:
                 continue
-            m.name = _makeName(n, prefixes)
+            m.name = _makeName(n, prefixes, namedict)
             memlist.append(m)
 
     # handle the case where a named signal appears in a list also by giving
@@ -1272,8 +1278,10 @@ def _analyzeTopFunc(top_inst, func, *args, **kwargs):
             continue
         for attr, attrobj in vars(obj).items():
             if isinstance(attrobj, _Signal):
-                signame = name + '_' + attr
-                attrobj._name = signame
+                signame = attrobj._name
+                if not signame:
+                    signame = name + '_' + attr
+                    attrobj._name = signame
                 v.argdict[signame] = attrobj
                 v.argnames.append(signame)
 

myhdl/test/conversion/general/test_interfaces2.py

@@ -34,7 +34,7 @@ def m_test_intf(clock,reset,a,b,c):
     intfaa = Intf()
 
     gen_mod = m_modify(clock,reset,intfaa)
-    
+
     @always_seq(clock.posedge,reset=reset)
     def rtl_inc():
         intfa.x.next = intfa.x - 1
@@ -58,6 +58,25 @@ def m_test_intf(clock,reset,a,b,c):
     return gen_mod,rtl_inc,rtl_combine
 
 
+def name_conflict_after_replace(clock, reset, a, a_x):
+    a_x_0 = [Signal(intbv(0)[len(a_x):]) for i in range(8)]
+
+    @always_seq(clock.posedge, reset=reset)
+    def logic():
+        a.x.next = a_x
+        a_x.next = a_x_0[1]
+
+    return logic
+
+
+def test_name_conflict_after_replace():
+    clock = Signal(False)
+    reset = ResetSignal(0, active=0, async=False)
+    a = Intf()
+    a_x = Signal(intbv(0)[len(a.x):])
+    assert conversion.analyze(name_conflict_after_replace, clock, reset, a, a_x) == 0
+
+
 def c_testbench():
     clock = Signal(bool(0))
     reset = ResetSignal(0, active=0, async=False)
@@ -82,9 +101,9 @@ def c_testbench():
         for ii in range(17):
             print("a: x=%d y=%d z=%d"%(a.x,a.y,a.z))
             print("b: x=%d y=%d z=%d"%(b.x,b.y,b.z))
-            print("c: x=%d y=%d z=%d"%(c.x,c.y,c.z))            
+            print("c: x=%d y=%d z=%d"%(c.x,c.y,c.z))
             yield clock.posedge
-            
+
         raise StopSimulation
 
     return tb_dut,tb_clk,tb_stim
@@ -102,4 +121,3 @@ if __name__ == '__main__':
     verify.simulator = analyze.simulator = sys.argv[1]
     Simulation(c_testbench()).run()
     print(verify(c_testbench))
-