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Moved to using the VHDL 2008 literals for the initial values.

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This commit is contained in:
Henry Gomersall 2016-03-24 16:01:45 +00:00
parent e64ae384b7
commit eaf8310e04
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GPG Key ID: 67F4313D73CED5A6
3 changed files with 21 additions and 15 deletions
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14
myhdl/conversion/_toVHDL.py
View File

@ -113,7 +113,7 @@ class _ToVHDLConvertor(object):
"use_clauses",
"architecture",
"std_logic_ports",
"no_initial_value"
"no_initial_values"
)
def __init__(self):
@ -127,7 +127,7 @@ class _ToVHDLConvertor(object):
self.use_clauses = None
self.architecture = "MyHDL"
self.std_logic_ports = False
self.no_initial_value = True
self.no_initial_values = True
def __call__(self, func, *args, **kwargs):
global _converting
@ -416,17 +416,19 @@ def _writeSigDecls(f, intf, siglist, memlist):
sig_vhdl_obj = inferVhdlObj(s)
if toVHDL.no_initial_value:
if toVHDL.no_initial_values:
val_str = ""
else:
if isinstance(sig_vhdl_obj, vhd_std_logic):
# Single bit
val_str = " := '%s'" % int(s._init)
elif isinstance(sig_vhdl_obj, vhd_int):
val_str = " := %s" % s._init
else:
val_str = ' := "%s"' % bin(s._init, sig_vhdl_obj.size)
val_str = ' := %dX"%s"' % (
sig_vhdl_obj.size, str(s._init))
print("signal %s: %s%s%s;" % (s._name, p, r, val_str), file=f)
elif s._read:

6
myhdl/conversion/_toVerilog.py
View File

@ -108,7 +108,7 @@ class _ToVerilogConvertor(object):
"no_testbench",
"portmap",
"trace",
"no_initial_value"
"no_initial_values"
)
def __init__(self):
@ -122,7 +122,7 @@ class _ToVerilogConvertor(object):
self.no_myhdl_header = False
self.no_testbench = False
self.trace = False
self.no_initial_value = True
self.no_initial_values = True
def __call__(self, func, *args, **kwargs):
global _converting
@ -331,7 +331,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
# the following line implements initial value assignments
# don't initial value "wire", inital assignment to a wire
# equates to a continuous assignment [reference]
if toVerilog.no_initial_value or k == 'wire':
if toVerilog.no_initial_values or k == 'wire':
print("%s %s%s%s;" % (k, p, r, s._name), file=f)
else:
print("%s %s%s%s = %s;" %

16
myhdl/test/conversion/general/test_initial_values.py
View File

@ -63,17 +63,17 @@ def initial_value_bench(initial_val, change_input_signal):
return clkgen, output_driver, drive_and_check, output_writer
def runner(initial_val, change_input_signal=False):
pre_toVerilog_no_initial_value = toVerilog.no_initial_value
pre_toVHDL_no_initial_value = toVerilog.no_initial_value
pre_toVerilog_no_initial_values = toVerilog.no_initial_values
pre_toVHDL_no_initial_values = toVerilog.no_initial_values
toVerilog.no_initial_value = False
toVHDL.no_initial_value = False
toVerilog.no_initial_values = False
toVHDL.no_initial_values = False
assert conversion.verify(
initial_value_bench, initial_val, change_input_signal) == 0
toVerilog.no_initial_value = pre_toVerilog_no_initial_value
toVHDL.no_initial_value = pre_toVHDL_no_initial_value
toVerilog.no_initial_values = pre_toVerilog_no_initial_values
toVHDL.no_initial_values = pre_toVHDL_no_initial_values
def test_unsigned():
'''The correct initial value should be used for unsigned type signal.
@ -135,3 +135,7 @@ def test_init_user():
runner(initial_val, change_input_signal=True)
if __name__ == "__main__":
test_long_signals()