From eaf8310e04e853fc053a339745ec50e259cf3602 Mon Sep 17 00:00:00 2001 From: Henry Gomersall Date: Thu, 24 Mar 2016 16:01:45 +0000 Subject: [PATCH] Moved to using the VHDL 2008 literals for the initial values. --- myhdl/conversion/_toVHDL.py | 14 ++++++++------ myhdl/conversion/_toVerilog.py | 6 +++--- .../conversion/general/test_initial_values.py | 16 ++++++++++------ 3 files changed, 21 insertions(+), 15 deletions(-) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index ccb17914..0e67d194 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -113,7 +113,7 @@ class _ToVHDLConvertor(object): "use_clauses", "architecture", "std_logic_ports", - "no_initial_value" + "no_initial_values" ) def __init__(self): @@ -127,7 +127,7 @@ class _ToVHDLConvertor(object): self.use_clauses = None self.architecture = "MyHDL" self.std_logic_ports = False - self.no_initial_value = True + self.no_initial_values = True def __call__(self, func, *args, **kwargs): global _converting @@ -416,17 +416,19 @@ def _writeSigDecls(f, intf, siglist, memlist): sig_vhdl_obj = inferVhdlObj(s) - if toVHDL.no_initial_value: + if toVHDL.no_initial_values: val_str = "" else: - + if isinstance(sig_vhdl_obj, vhd_std_logic): + # Single bit val_str = " := '%s'" % int(s._init) elif isinstance(sig_vhdl_obj, vhd_int): val_str = " := %s" % s._init else: - val_str = ' := "%s"' % bin(s._init, sig_vhdl_obj.size) - + val_str = ' := %dX"%s"' % ( + sig_vhdl_obj.size, str(s._init)) + print("signal %s: %s%s%s;" % (s._name, p, r, val_str), file=f) elif s._read: diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 15e6be96..1adb8aa7 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -108,7 +108,7 @@ class _ToVerilogConvertor(object): "no_testbench", "portmap", "trace", - "no_initial_value" + "no_initial_values" ) def __init__(self): @@ -122,7 +122,7 @@ class _ToVerilogConvertor(object): self.no_myhdl_header = False self.no_testbench = False self.trace = False - self.no_initial_value = True + self.no_initial_values = True def __call__(self, func, *args, **kwargs): global _converting @@ -331,7 +331,7 @@ def _writeSigDecls(f, intf, siglist, memlist): # the following line implements initial value assignments # don't initial value "wire", inital assignment to a wire # equates to a continuous assignment [reference] - if toVerilog.no_initial_value or k == 'wire': + if toVerilog.no_initial_values or k == 'wire': print("%s %s%s%s;" % (k, p, r, s._name), file=f) else: print("%s %s%s%s = %s;" % diff --git a/myhdl/test/conversion/general/test_initial_values.py b/myhdl/test/conversion/general/test_initial_values.py index 74ae932b..062364c8 100644 --- a/myhdl/test/conversion/general/test_initial_values.py +++ b/myhdl/test/conversion/general/test_initial_values.py @@ -63,17 +63,17 @@ def initial_value_bench(initial_val, change_input_signal): return clkgen, output_driver, drive_and_check, output_writer def runner(initial_val, change_input_signal=False): - pre_toVerilog_no_initial_value = toVerilog.no_initial_value - pre_toVHDL_no_initial_value = toVerilog.no_initial_value + pre_toVerilog_no_initial_values = toVerilog.no_initial_values + pre_toVHDL_no_initial_values = toVerilog.no_initial_values - toVerilog.no_initial_value = False - toVHDL.no_initial_value = False + toVerilog.no_initial_values = False + toVHDL.no_initial_values = False assert conversion.verify( initial_value_bench, initial_val, change_input_signal) == 0 - toVerilog.no_initial_value = pre_toVerilog_no_initial_value - toVHDL.no_initial_value = pre_toVHDL_no_initial_value + toVerilog.no_initial_values = pre_toVerilog_no_initial_values + toVHDL.no_initial_values = pre_toVHDL_no_initial_values def test_unsigned(): '''The correct initial value should be used for unsigned type signal. @@ -135,3 +135,7 @@ def test_init_user(): runner(initial_val, change_input_signal=True) +if __name__ == "__main__": + test_long_signals() + +