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use print_function in core modules

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This commit is contained in:
Keerthan Jaic 2015-02-01 19:52:25 -05:00
parent f4efd526ae
commit ec2d78c256
5 changed files with 35 additions and 30 deletions
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9
myhdl/_Signal.py
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@ -27,6 +27,7 @@ negedge -- callable to model a falling edge on a signal in a yield statement
"""
from __future__ import absolute_import
from __future__ import print_function
from inspect import currentframe, getouterframes
from copy import copy, deepcopy
@ -296,16 +297,16 @@ class _Signal(object):
# vcd print methods
def _printVcdStr(self):
print >> sim._tf, "s%s %s" % (str(self._val), self._code)
print("s%s %s" % (str(self._val), self._code), file=sim._tf)
def _printVcdHex(self):
print >> sim._tf, "s%s %s" % (hex(self._val), self._code)
print("s%s %s" % (hex(self._val), self._code), file=sim._tf)
def _printVcdBit(self):
print >> sim._tf, "%d%s" % (self._val, self._code)
print("%d%s" % (self._val, self._code), file=sim._tf)
def _printVcdVec(self):
print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code)
print("b%s %s" % (bin(self._val, self._nrbits), self._code), file=sim._tf)
### use call interface for shadow signals ###
def __call__(self, left, right=None):

3
myhdl/_Simulation.py
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@ -19,6 +19,7 @@
""" Module that provides the Simulation class """
from __future__ import absolute_import
from __future__ import print_function
import sys
@ -159,7 +160,7 @@ class Simulation(object):
_futureEvents.sort()
t = _simulator._time = _futureEvents[0][0]
if tracing:
print >> tracefile, "#%s" % t
print("#%s" % t, file=tracefile)
if cosim:
cosim._put(t)
while _futureEvents:

3
myhdl/__init__.py
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@ -50,6 +50,7 @@ toVerilog -- function that converts a design to Verilog
"""
from __future__ import absolute_import
from __future__ import print_function
__version__ = "0.9dev"
@ -107,7 +108,7 @@ class ToVHDLWarning(ConversionWarning):
# warnings.filterwarnings('always', r".*", ToVerilogWarning)
def showwarning(message, category, filename, lineno, *args):
print >> sys.stderr, "** %s: %s" % (category.__name__, message)
print("** %s: %s" % (category.__name__, message), file=sys.stderr)
warnings.showwarning = showwarning

47
myhdl/_traceSignals.py
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@ -21,6 +21,7 @@
"""
from __future__ import absolute_import
from __future__ import print_function
@ -119,16 +120,16 @@ def _namecode(n):
return code
def _writeVcdHeader(f, timescale):
print >> f, "$date"
print >> f, " %s" % time.asctime()
print >> f, "$end"
print >> f, "$version"
print >> f, " MyHDL %s" % __version__
print >> f, "$end"
print >> f, "$timescale"
print >> f, " %s" % timescale
print >> f, "$end"
print >> f
print("$date", file=f)
print(" %s" % time.asctime(), file=f)
print("$end", file=f)
print("$version", file=f)
print(" MyHDL %s" % __version__, file=f)
print("$end", file=f)
print("$timescale", file=f)
print(" %s" % timescale, file=f)
print("$end", file=f)
print(file=f)
def _writeVcdSigs(f, hierarchy, tracelists):
curlevel = 0
@ -144,8 +145,8 @@ def _writeVcdSigs(f, hierarchy, tracelists):
assert(delta >= -1)
if delta >= 0:
for i in range(delta + 1):
print >> f, "$upscope $end"
print >> f, "$scope module %s $end" % name
print("$upscope $end", file=f)
print("$scope module %s $end" % name, file=f)
for n, s in sigdict.items():
if s._val is None:
raise ValueError("%s of module %s has no initial value" % (n, name))
@ -157,11 +158,11 @@ def _writeVcdSigs(f, hierarchy, tracelists):
# use real for enum strings
if w and not isinstance(s._val, EnumItemType):
if w == 1:
print >> f, "$var reg 1 %s %s $end" % (s._code, n)
print("$var reg 1 %s %s $end" % (s._code, n), file=f)
else:
print >> f, "$var reg %s %s %s $end" % (w, s._code, n)
print("$var reg %s %s %s $end" % (w, s._code, n), file=f)
else:
print >> f, "$var real 1 %s %s $end" % (s._code, n)
print("$var real 1 %s %s $end" % (s._code, n), file=f)
# Memory dump by Frederik Teichert, http://teichert-ing.de, date: 2011.03.28
# The Value Change Dump standard doesn't support multidimensional arrays so
# all memories are flattened and renamed.
@ -178,20 +179,20 @@ def _writeVcdSigs(f, hierarchy, tracelists):
w = s._nrbits
if w:
if w == 1:
print >> f, "$var reg 1 %s %s(%i) $end" % (s._code, n, memindex)
print("$var reg 1 %s %s(%i) $end" % (s._code, n, memindex), file=f)
else:
print >> f, "$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex)
print("$var reg %s %s %s(%i) $end" % (w, s._code, n, memindex), file=f)
else:
print >> f, "$var real 1 %s %s(%i) $end" % (s._code, n, memindex)
print("$var real 1 %s %s(%i) $end" % (s._code, n, memindex), file=f)
memindex += 1
for i in range(curlevel):
print >> f, "$upscope $end"
print >> f
print >> f, "$enddefinitions $end"
print >> f, "$dumpvars"
print("$upscope $end", file=f)
print(file=f)
print("$enddefinitions $end", file=f)
print("$dumpvars", file=f)
for s in siglist:
s._printVcd() # initial value
print >> f, "$end"
print("$end", file=f)

3
myhdl/_util.py
View File

@ -21,6 +21,7 @@
"""
from __future__ import absolute_import
from __future__ import print_function
import ast
@ -37,7 +38,7 @@ def _printExcInfo():
# msg = msg[msg.rindex('.')+1:]
if str(value):
msg += ": %s" % value
print >> sys.stderr, msg
print(msg, file=sys.stderr)
_isGenFunc = inspect.isgeneratorfunction