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--HG--
branch : 0.9-dev
This commit is contained in:
Jan Decaluwe 2014-04-11 15:32:04 +02:00
commit ec61ef61e1
1 changed files with 1 additions and 1 deletions
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myhdl/conversion/_toVerilog.py
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@ -1272,7 +1272,7 @@ def _convertInitVal(reg, init):
if tipe is bool:
v = '1' if init else '0'
elif tipe is intbv:
v = "%s" % init
v = "%s" % init if init is not None else "'bz"
else:
assert isinstance(init, EnumItemType)
v = init._toVerilog()