FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

merge from default

Browse Source 
--HG--
branch : 0.9-dev
This commit is contained in:
Jan Decaluwe 2014-04-11 15:32:04 +02:00
commit ec61ef61e1
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
myhdl/conversion/_toVerilog.py
View File

@ -1272,7 +1272,7 @@ def _convertInitVal(reg, init):
if tipe is bool: if tipe is bool:
v = '1' if init else '0' v = '1' if init else '0'
elif tipe is intbv: elif tipe is intbv:
v = "%s" % init v = "%s" % init if init is not None else "'bz"
else: else:
assert isinstance(init, EnumItemType) assert isinstance(init, EnumItemType)
v = init._toVerilog() v = init._toVerilog()