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Code Issues Projects Releases Wiki Activity

Cleaning up tests: (#412)

Browse Source 
* Cleaning up tests:
removing wildcard imports
correcting indents
remving as much warnings as possible: mostly unused variables

* TestInferWaiter: correct mismatch in number of arguments

* replacing `for __` inside generator with `for dummy`
cleaning ud 'bugs' section too

* repaired some over-optimistic "Verschlimmbesserungen"

* some more repairs of new *Vershlimwbesserungen* - literally *improvements that make things worse* :)
This commit is contained in:
Josy Boelen 2023-04-10 13:08:57 +01:00 committed by GitHub
parent 4f8b1df02c
commit ef206f072e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
114 changed files with 3091 additions and 2564 deletions
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16
myhdl/test/bugs/test_bug_1740778.py
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@ -1,24 +1,20 @@
import sys
import os
path = os.path
import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl.conversion import verify
from myhdl import (block, Signal, intbv, instance, delay)
ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1)
@block
def bug_1740778 ():
""" Conversion of min and max attribute.
"""
s = Signal(intbv(0, min=-13, max=46))
@instance
def logic():
v = intbv(0, min=-15, max=45)
@ -28,10 +24,10 @@ def bug_1740778 ():
print(s.val)
print(s.min)
print(s.max)
return logic
def test_bug_1740778 ():
def test_bug_1740778 ():
assert bug_1740778().verify_convert() == 0

14
myhdl/test/bugs/test_bug_1835792.py
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@ -1,31 +1,29 @@
import sys
import os
path = os.path
import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, intbv, instance, delay)
ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1)
@block
def bug_1835792 ():
""" Semicolon conversion
"""
@instance
def logic():
v = intbv(0, min=-15, max=45)
yield delay(10)
print(v.min);
print(v.max);
return logic
def test_bug_1835792 ():
def test_bug_1835792 ():
assert bug_1835792().verify_convert() == 0

14
myhdl/test/bugs/test_bug_1835797.py
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@ -1,21 +1,19 @@
import sys
import os
path = os.path
import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, intbv, instance, delay)
ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1)
@block
def bug_1835797():
""" Docstring in the middle.
"""
@instance
def logic():
v = intbv(0, min=-15, max=45)
@ -23,10 +21,10 @@ def bug_1835797():
yield delay(10)
print(v.min)
print(v.max)
return logic
def test_bug_1835797():
def test_bug_1835797():
assert bug_1835797().verify_convert() == 0

16
myhdl/test/bugs/test_bug_1837003.py
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@ -1,22 +1,25 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, instances, always_comb)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
@block
def SubFunction_1837003(xout,yout,xin,yin):
def SubFunction_1837003(xout, yout, xin, yin):
@always_comb
def logic():
x = 4
y = 2
xout.next = xin
yout.next = yin
return instances()
#def Function_1837003(xout,yout,x,y):
# def Function_1837003(xout,yout,x,y):
# return SubFunction_1837003(xout,yout,x,y)
x = Signal(bool(0))
y = Signal(bool(0))
xout = Signal(bool(0))
@ -24,9 +27,10 @@ yout = Signal(bool(0))
xin = Signal(bool(0))
yin = Signal(bool(0))
def test_bug_1837003():
try:
SubFunction_1837003(xout,yout,x,y).convert(hdl='Verilog')
SubFunction_1837003(xout, yout, x, y).convert(hdl='Verilog')
except ConversionError as e:
assert e.kind == _error.ShadowingVar
else:

8
myhdl/test/bugs/test_bug_28.py
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@ -1,16 +1,20 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, always_comb)
@block
def bug_28(dout, channel):
@always_comb
def comb():
dout.next = 0x8030 + (channel << 10)
return comb
dout = Signal(intbv(0)[16:0])
channel = Signal(intbv(0)[4:0])
def test_bug_28():
try:
bug_28(dout, channel).convert(hdl='VHDL')

8
myhdl/test/bugs/test_bug_3529686.py
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@ -1,5 +1,5 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, always)
@block
def bug_3529686(clr, clk, run, ack, serialout):
@ -7,14 +7,14 @@ def bug_3529686(clr, clk, run, ack, serialout):
@always(clk.posedge, clr.posedge)
def fsm():
if (clr == 0):
serialout.next = 0
serialout.next = 0
else:
if (ack == 0):
serialout.next = 0
elif (run == 1):
serialout.next = 1
return fsm
return fsm
clr, clk, run, ack, serialout = [Signal(bool()) for i in range(5)]

8
myhdl/test/bugs/test_bug_3577799.py
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@ -1,5 +1,5 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, instance)
@block
def bug_3577799 (
@ -22,9 +22,10 @@ def bug_3577799 (
if count < depth:
rd_data.next = wr_data
count = count + 1
return seq
depth = 8
clk = Signal(bool(0))
reset_clk = Signal(bool(0))
@ -32,5 +33,6 @@ wr_data = Signal(intbv(0)[16:])
wr = Signal(bool(0))
rd_data = Signal(intbv(0)[16:])
def test_bug_3577799():
assert bug_3577799(clk, reset_clk, wr_data, wr, rd_data).analyze_convert() == 0

10
myhdl/test/bugs/test_bug_39.py
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@ -1,5 +1,5 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, instance, always_comb, delay)
@block
def dut():
@ -9,7 +9,7 @@ def dut():
b = Signal(intbv(0, min=0, max=256))
c = Signal(intbv(0, min=0, max=256))
d = Signal(intbv(0, min=0, max=256))
@always_comb
def logic():
rx.next = a + b - (c + d)
@ -20,7 +20,7 @@ def dut():
b.next = 0
c.next = 0
d.next = 0
for i in range(100):
for dummy in range(100):
yield delay(10)
print(rx)
a.next = (a + 37) % 256
@ -30,7 +30,7 @@ def dut():
return logic, check
def test_bug_39():
assert dut().verify_convert() == 0

10
myhdl/test/bugs/test_bug_42.py
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@ -1,7 +1,5 @@
#! /usr/bin/env python
from myhdl import (block, Signal, intbv, always_comb)
import myhdl
from myhdl import *
@block
def module_42(sigin, sigout):
@ -9,16 +7,18 @@ def module_42(sigin, sigout):
# Using @always(sigin) only warns, but using @always_comp breaks.
# The reason is that len(sigout) is interpreted as sigout being used as
# an input.
#@always(sigin)
# @always(sigin)
@always_comb
def output():
sigout.next = sigin[len(sigout):]
sigout.next = sigin[len(sigout):]
return output
sigin = Signal(intbv(0)[2:])
sigout = Signal(intbv(0)[2:])
def test_bug_42():
module_42(sigin, sigout).convert(hdl='VHDL')

10
myhdl/test/bugs/test_bug_42_2.py
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@ -1,7 +1,5 @@
#! /usr/bin/env python
from myhdl import (block, Signal, intbv, always)
import myhdl
from myhdl import *
@block
def module42_2(sigin, sigout):
@ -11,16 +9,18 @@ def module42_2(sigin, sigout):
# an input.
@always(sigin)
def output():
sigout.next = sigin[len(sigout):]
sigout.next = sigin[len(sigout):]
return output
sigin = Signal(intbv(0)[2:])
sigout = Signal(intbv(0)[2:])
def test_bug_42_2():
module42_2(sigin, sigout).convert(hdl='VHDL')
module42_2(sigin, sigout).convert(hdl='VHDL')

16
myhdl/test/bugs/test_bug_43.py
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@ -1,26 +1,24 @@
#! /usr/bin/env python
from myhdl import (block, Signal, intbv, always_comb, concat)
import myhdl
from myhdl import *
@block
def bug_43(sigin, sigout):
@always_comb
def output():
# This does not generate correct VHDL code (resize is missing)
sigout.next = concat(sigin[0], sigin[2])
# This does not generate correct VHDL code (resize is missing)
sigout.next = concat(sigin[0], sigin[2])
# The following does work:
tmp = concat(sigin[0], sigin[2])
sigout.next = tmp
# The following does work:
tmp = concat(sigin[0], sigin[2])
sigout.next = tmp
return output
def test_bug_43():
sigin = Signal(intbv(0)[4:])
sigout = Signal(intbv(0)[4:])
assert bug_43(sigin, sigout).analyze_convert() == 0

27
myhdl/test/bugs/test_bug_44.py
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@ -1,40 +1,45 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, always, modbv, delay, instance, StopSimulation, instances, Simulation)
WIDTH=4
WIDTH = 4
clk = Signal(bool(0))
x = Signal(modbv(0)[WIDTH:])
y = Signal(modbv(0)[WIDTH:])
z = Signal(modbv(0)[WIDTH:])
x = Signal(modbv(0)[WIDTH:])
y = Signal(modbv(0)[WIDTH:])
z = Signal(modbv(0)[WIDTH:])
@always(delay(5))
def tb_clk_gen():
clk.next = not clk
@always(clk.posedge)
def inc():
y.next = x + 1
@always(clk.posedge)
def dec():
z.next = x - 1
@instance
def tb_stimulus():
# My logic happens on posedge, so I'll perform all checks on negedge.
yield clk.negedge
for x_val in range(-2**WIDTH, 2**WIDTH):
#print('x_val={} x.next={}'.format(x_val, x_val % 2**WIDTH))
x.next = x_val % 2**WIDTH
for x_val in range(-2 ** WIDTH, 2 ** WIDTH):
# print('x_val={} x.next={}'.format(x_val, x_val % 2**WIDTH))
x.next = x_val % 2 ** WIDTH
yield clk.negedge
assert y==(x_val+1)%2**WIDTH, 'y={} but expected {}'.format(y, (x_val+1)%2**WIDTH)
assert z==(x_val-1)%2**WIDTH, 'z={} but expected {}'.format(z, (x_val-1)%2**WIDTH)
assert y == (x_val + 1) % 2 ** WIDTH, 'y={} but expected {}'.format(y, (x_val + 1) % 2 ** WIDTH)
assert z == (x_val - 1) % 2 ** WIDTH, 'z={} but expected {}'.format(z, (x_val - 1) % 2 ** WIDTH)
print('OK!')
raise StopSimulation
tb = instances()
def test_bug_44():
print(instances())
Simulation(tb).run()

14
myhdl/test/bugs/test_bug_aj1s.py
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@ -1,5 +1,5 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, instance, delay)
@block
def dut():
@ -9,14 +9,14 @@ def dut():
@instance
def seq():
count.next = 50
for i in range(300):
for dummy in range(300):
yield delay(10)
print(count)
if count-1 < 0:
count.next = 97
if count - 1 < 0:
count.next = 97
else:
count.next = count-1
count.next = count - 1
return seq

14
myhdl/test/bugs/test_bug_boolconst.py
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@ -1,10 +1,10 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, always_comb)
INT_CONDITION_0 = 0
INT_CONDITION_1 = 1
BOOL_CONDITION_0 = False
BOOL_CONDITION_1 = True
INT_CONDITION_0 = 0
INT_CONDITION_1 = 1
BOOL_CONDITION_0 = False
BOOL_CONDITION_1 = True
@block
def bug_boolconst(sigin, sigout):
@ -31,10 +31,10 @@ def bug_boolconst(sigin, sigout):
return output
def test_bug_boolconst():
sigin = Signal(bool())
sigout = Signal(bool())
assert bug_boolconst(sigin, sigout).analyze_convert() == 0

15
myhdl/test/bugs/test_bug_boolop.py
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@ -1,5 +1,5 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, always_seq, ResetSignal, always)
@block
def gray_counter_bug_boolop (clk, reset, enable, gray_count):
@ -8,13 +8,12 @@ def gray_counter_bug_boolop (clk, reset, enable, gray_count):
no_ones_below = Signal(intbv(0)[10:])
q_msb = Signal(bool(0))
@always_seq(clk.posedge, reset=reset)
def seq():
if enable:
q.next[0] = not q[0]
for i in range(1, 9):
q.next[i] = q[i] ^ (q[i-1] and no_ones_below[i-1])
q.next[i] = q[i] ^ (q[i - 1] and no_ones_below[i - 1])
q.next[8] = q[8] ^ (q_msb and no_ones_below[7])
@always(q, no_ones_below)
@ -22,16 +21,18 @@ def gray_counter_bug_boolop (clk, reset, enable, gray_count):
q_msb.next = q[8] or q[7]
no_ones_below.next[0] = 1
for j in range(1, 10):
no_ones_below.next[j] = no_ones_below[j-1] and not q[j-1]
no_ones_below.next[j] = no_ones_below[j - 1] and not q[j - 1]
gray_count.next[8:] = q[9:1]
return comb, seq
clk = Signal(bool(0))
reset = ResetSignal(0, active=0, isasync=True)
enable = Signal(bool(0))
gray_count = Signal(intbv(0)[8:])
def test_bug_boolop():
try:
gray_counter_bug_boolop(clk, reset, enable, gray_count).convert(hdl='Verilog')

4
myhdl/test/bugs/test_bug_enum_toVHDL.py
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@ -1,9 +1,9 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, enum, always_comb)
# t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot')
t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE')
@block
def pcie_legacyint_next_state_logic(state_i, next_state_o, next_state_en_o, interrupt_pending_i, interrupt_assert_o):

4
myhdl/test/bugs/test_bug_enum_toVHDL_2.py
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@ -1,8 +1,8 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, enum, always_comb)
t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot')
@block
def pcie_legacyint_next_state_logic_2(state_i, next_state_o, next_state_en_o, interrupt_pending_i, interrupt_assert_o):

34
myhdl/test/bugs/test_issue_10.py
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@ -1,24 +1,26 @@
#!/usr/bin/python2.7-32
# -*- coding: utf-8 -*-
import myhdl
from myhdl import (Signal, intbv, concat)
def unsigned(width, value=0, cls=myhdl.intbv):
"""Create an unsigned signal based on a bitvector with the
specified width and initial value.
"""
return myhdl.Signal(cls(value, 0, 2**width))
def signed(width, value=0, cls=myhdl.intbv):
"""Create an signed signal based on a bitvector with the
specified width and initial value.
"""
return myhdl.Signal(cls(value, -2**(width-1), 2**(width-1)))
def unsigned(width, value=0, cls=intbv):
"""Create an unsigned signal based on a bitvector with the
specified width and initial value.
"""
return Signal(cls(value, 0, 2 ** width))
def signed(width, value=0, cls=intbv):
"""Create an signed signal based on a bitvector with the
specified width and initial value.
"""
return Signal(cls(value, -2 ** (width - 1), 2 ** (width - 1)))
a = unsigned(4, 8)
b = signed(28, -3)
#print "%08X" % myhdl.concat(a, b)
#print hex(myhdl.concat(a, b))
# print "%08X" % myhdl.concat(a, b)
# print hex(myhdl.concat(a, b))
def test_issue_10():
assert myhdl.concat(a, b) == 0x8ffffffd
assert concat(a, b) == 0x8ffffffd

30
myhdl/test/bugs/test_issue_104.py
View File

@ -3,18 +3,20 @@ from myhdl import Simulation, delay, SimulationError, instance, now, block
from myhdl._Simulation import _error
from helpers import raises_kind
@block
def dut():
@instance
def tbstim():
yield delay(10)
print("{0:<8d} ".format(now()))
yield delay(1000)
print("{0:<8d} ".format(now()))
for _ in range(10):
yield delay(1000)
return tbstim
@instance
def tbstim():
yield delay(10)
print("{0:<8d} ".format(now()))
yield delay(1000)
print("{0:<8d} ".format(now()))
for _ in range(10):
yield delay(1000)
return tbstim
def issue_104_quit_method():
@ -23,20 +25,22 @@ def issue_104_quit_method():
sim.run(500)
sim.quit()
return sim._finished
def issue_104_multiple_instance():
sim1 = Simulation(dut())
sim1.run(1000)
# sim1 is "puased"
# sim1 is "paused"
# try and create a second, third, forth simulation instance
for ii in range(4):
for dummy in range(4):
with raises_kind(SimulationError, _error.MultipleSim):
another_sim = Simulation(dut())
another_sim = Simulation(dut())
# generating more sims should have failed
sim1.run(1000)
sim1.quit()
def test_issue_104():
assert issue_104_quit_method() == True

17
myhdl/test/bugs/test_issue_10_2.py
View File

@ -1,26 +1,27 @@
#!/usr/bin/env python
# -*- coding: utf-8 -*-
"""Failed VHDL code example
"""
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, instance, delay, concat)
def unsigned(width, value=0, cls=intbv):
"""Create an unsigned signal based on a bitvector with the
specified width and initial value.
"""
return Signal(cls(value, 0, 2**width))
return Signal(cls(value, 0, 2 ** width))
def signed(width, value=0, cls=intbv):
"""Create an signed signal based on a bitvector with the
specified width and initial value.
"""
return Signal(cls(value, -2**(width-1), 2**(width-1)))
return Signal(cls(value, -2 ** (width - 1), 2 ** (width - 1)))
flags = unsigned(4)
position = signed(28)
@block
def Logic(flags, position):
@ -28,13 +29,15 @@ def Logic(flags, position):
@instance
def doit():
flags.next = 4
flags.next = 4
position.next = 28
yield delay(10)
conc.next = concat(flags, position)
yield delay(10)
print(conc)
print(conc)
return doit
def test_issue_10_2():
assert Logic(flags, position).verify_convert() == 0

70
myhdl/test/bugs/test_issue_117.py
View File

@ -1,50 +1,52 @@
import myhdl
from myhdl import *
#from myhdl.conversion import analyze
from myhdl import (block, Signal, intbv, always, concat, toVerilog, toVHDL)
from myhdl.conversion import analyze
@block
def issue_117(clk, sdi, pdo, sel, const=False):
assert isinstance(const, (bool, intbv))
delay_reg = Signal(intbv(0)[8:])
rlen = len(pdo)
plen = 1 if isinstance(const, bool) else len(const)
@always(clk.posedge)
def rtl():
if sel == 0:
delay_reg.next = concat(const, delay_reg[rlen-plen-1:1], sdi)
elif sel == 1:
delay_reg.next = concat(delay_reg[rlen-1:plen+1], const, sdi)
elif sel == 2:
delay_reg.next = concat(delay_reg[rlen-1:plen+1], sdi, const)
pdo.next = delay_reg
return rtl
assert isinstance(const, (bool, intbv))
delay_reg = Signal(intbv(0)[8:])
rlen = len(pdo)
plen = 1 if isinstance(const, bool) else len(const)
@always(clk.posedge)
def rtl():
if sel == 0:
delay_reg.next = concat(const, delay_reg[rlen - plen - 1:1], sdi)
elif sel == 1:
delay_reg.next = concat(delay_reg[rlen - 1:plen + 1], const, sdi)
elif sel == 2:
delay_reg.next = concat(delay_reg[rlen - 1:plen + 1], sdi, const)
pdo.next = delay_reg
return rtl
def test_issue_117_1():
clk, sdi = [Signal(bool(0)) for _ in range(2)]
pdo = Signal(intbv(0)[8:])
sel = Signal(intbv(0, min=0, max=3))
toVHDL.name = toVerilog.name = 'issue_117_1'
assert issue_117(clk, sdi, pdo, sel, const=bool(0)).analyze_convert() == 0
clk, sdi = [Signal(bool(0)) for _ in range(2)]
pdo = Signal(intbv(0)[8:])
sel = Signal(intbv(0, min=0, max=3))
toVHDL.name = toVerilog.name = 'issue_117_1'
assert issue_117(clk, sdi, pdo, sel, const=bool(0)).analyze_convert() == 0
def test_issue_117_2():
clk, sdi = [Signal(bool(0)) for _ in range(2)]
pdo = Signal(intbv(0)[8:])
sel = Signal(intbv(0, min=0, max=3))
toVHDL.name = toVerilog.name = 'issue_117_2'
assert issue_117(clk, sdi, pdo, sel, const=False).analyze_convert() == 0
clk, sdi = [Signal(bool(0)) for _ in range(2)]
pdo = Signal(intbv(0)[8:])
sel = Signal(intbv(0, min=0, max=3))
toVHDL.name = toVerilog.name = 'issue_117_2'
assert issue_117(clk, sdi, pdo, sel, const=False).analyze_convert() == 0
def test_issue_117_3():
clk, sdi = [Signal(bool(0)) for _ in range(2)]
pdo = Signal(intbv(0)[8:])
sel = Signal(intbv(0, min=0, max=3))
toVHDL.name = toVerilog.name = 'issue_117_3'
assert issue_117(clk, sdi, pdo, sel, const=intbv(0)[1:]).analyze_convert() == 0
clk, sdi = [Signal(bool(0)) for _ in range(2)]
pdo = Signal(intbv(0)[8:])
sel = Signal(intbv(0, min=0, max=3))
toVHDL.name = toVerilog.name = 'issue_117_3'
assert issue_117(clk, sdi, pdo, sel, const=intbv(0)[1:]).analyze_convert() == 0
if __name__ == '__main__':
analyze.simulator='vlog'
analyze.simulator = 'vlog'
test_issue_117_1()

17
myhdl/test/bugs/test_issue_122.py
View File

@ -1,31 +1,34 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, instance, delay)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
@block
def issue_122(dout, i):
d = i*10+1
d = i * 10 + 1
@instance
def write():
dout[i].next = i
dout[i].next = i
yield delay(d)
print(int(dout[i]))
if i == 0:
return write
else:
inst = issue_122(dout, i-1)
inst = issue_122(dout, i - 1)
return write, inst
def tb_issue_122():
n = 7
dout = [Signal(intbv(0, min=0, max=n+1)) for i in range(n+1)]
dout = [Signal(intbv(0, min=0, max=n + 1)) for __ in range(n + 1)]
inst = issue_122(dout, n)
return inst
def test_issue_122():
try:
tb_issue_122().verify_convert()

183
myhdl/test/bugs/test_issue_127.py
View File

@ -5,10 +5,9 @@
import unittest
from random import randrange
from myhdl import Signal, intbv, \
always_comb, instance, \
delay, StopSimulation, block
from myhdl import (Signal, intbv,
always_comb, instance,
delay, StopSimulation, block)
ASCENDING = True
DESCENDING = False
@ -17,130 +16,132 @@ DESCENDING = False
# modules
@block
def compare(a_1, a_2, z_1, z_2, direction):
""" Combinatorial circuit with two input and two output signals.
Sorting to 'direction'. """
""" Combinatorial circuit with two input and two output signals.
Sorting to 'direction'. """
@always_comb
def logic():
''' Combinatorial logic '''
if direction == (a_1 > a_2):
z_1.next = a_2
z_2.next = a_1
else:
z_1.next = a_1
z_2.next = a_2
@always_comb
def logic():
''' Combinatorial logic '''
if direction == (a_1 > a_2):
z_1.next = a_2
z_2.next = a_1
else:
z_1.next = a_1
z_2.next = a_2
return logic
return logic
@block
def feedthru(in_a, out_z):
""" Equivalent of 'doing nothing'. """
""" Equivalent of 'doing nothing'. """
@always_comb
def logic():
''' Combinatorial logic '''
out_z.next = in_a
@always_comb
def logic():
''' Combinatorial logic '''
out_z.next = in_a
return logic
return logic
@block
def bitonic_merge(list_a, list_z, direction):
""" bitonicMerge:
Generates the output from the input list of signals.
Recursive. """
len_list = len(list_a)
half_len = len_list//2
width = len(list_a[0])
""" bitonicMerge:
Generates the output from the input list of signals.
Recursive. """
len_list = len(list_a)
half_len = len_list // 2
width = len(list_a[0])
if len_list > 1:
tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)]
if len_list > 1:
tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)]
comp = [compare(list_a[i], list_a[i+half_len], tmp[i], tmp[i+half_len], \
direction) for i in range(half_len)]
comp = [compare(list_a[i], list_a[i + half_len], tmp[i], tmp[i + half_len], \
direction) for i in range(half_len)]
lo_merge = bitonic_merge( tmp[:half_len], list_z[:half_len], direction )
hi_merge = bitonic_merge( tmp[half_len:], list_z[half_len:], direction )
lo_merge = bitonic_merge(tmp[:half_len], list_z[:half_len], direction)
hi_merge = bitonic_merge(tmp[half_len:], list_z[half_len:], direction)
return comp, lo_merge, hi_merge
else:
feed = feedthru(list_a[0], list_z[0])
return feed
return comp, lo_merge, hi_merge
else:
feed = feedthru(list_a[0], list_z[0])
return feed
@block
def bitonic_sort(list_a, list_z, direction):
""" bitonicSort:
Produces a bitonic sequence.
Recursive. """
len_list = len(list_a)
half_len = len_list//2
width = len(list_a[0])
""" bitonicSort:
Produces a bitonic sequence.
Recursive. """
len_list = len(list_a)
half_len = len_list // 2
width = len(list_a[0])
if len_list > 1:
tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)]
if len_list > 1:
tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)]
lo_sort = bitonic_sort( list_a[:half_len], tmp[:half_len], ASCENDING )
hi_sort = bitonic_sort( list_a[half_len:], tmp[half_len:], DESCENDING )
lo_sort = bitonic_sort(list_a[:half_len], tmp[:half_len], ASCENDING)
hi_sort = bitonic_sort(list_a[half_len:], tmp[half_len:], DESCENDING)
merge = bitonic_merge( tmp, list_z, direction )
return lo_sort, hi_sort, merge
else:
feed = feedthru(list_a[0], list_z[0])
return feed
merge = bitonic_merge(tmp, list_z, direction)
return lo_sort, hi_sort, merge
else:
feed = feedthru(list_a[0], list_z[0])
return feed
# tests
@block
def array8sorter_127(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7):
''' Sort Array with 8 values '''
''' Sort Array with 8 values '''
list_a = [a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7]
list_z = [z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7]
list_a = [a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7]
list_z = [z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7]
sort = bitonic_sort(list_a, list_z, ASCENDING)
return sort
sort = bitonic_sort(list_a, list_z, ASCENDING)
return sort
class TestBitonicSort(unittest.TestCase):
''' Test class for bitonic sort '''
''' Test class for bitonic sort '''
def test_sort(self):
""" Check the functionality of the bitonic sort """
length = 8
width = 4
def test_sort(self):
""" Check the functionality of the bitonic sort """
length = 8
width = 4
def test_impl():
''' test implementation '''
inputs = [ Signal(intbv(0)[width:]) for _ in range(length) ]
outputs = [ Signal(intbv(0)[width:]) for _ in range(length) ]
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7 = outputs
a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7 = inputs
def test_impl():
''' test implementation '''
inputs = [ Signal(intbv(0)[width:]) for _ in range(length) ]
outputs = [ Signal(intbv(0)[width:]) for _ in range(length) ]
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7 = outputs
a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7 = inputs
inst = array8sorter_127(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7)
@instance
def check():
''' testbench input and validation '''
for i in range(100):
data = [randrange(2**width) for i in range(length)]
for i in range(length):
inputs[i].next = data[i]
yield delay(10)
data.sort()
self.assertEqual(data, outputs, 'wrong data')
raise StopSimulation
return inst, check
inst = array8sorter_127(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7)
@instance
def check():
''' testbench input and validation '''
for dummy in range(100):
data = [randrange(2 ** width) for dummy in range(length)]
for i in range(length):
inputs[i].next = data[i]
yield delay(10)
data.sort()
self.assertEqual(data, outputs, 'wrong data')
raise StopSimulation
return inst, check
# convert
def test_issue_127():
''' Convert to VHDL '''
length = 8
width = 4
sigs = [Signal(intbv(0)[width:]) for _ in range(2*length)]
array8sorter_127(*sigs).convert(hdl='VHDL')
def test_issue_127():
''' Convert to VHDL '''
length = 8
width = 4
sigs = [Signal(intbv(0)[width:]) for _ in range(2 * length)]
array8sorter_127(*sigs).convert(hdl='VHDL')

16
myhdl/test/bugs/test_issue_13.py
View File

@ -1,5 +1,6 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, downrange, always_seq, concat, ResetSignal)
@block
def issue_13(reset, clk, d, en, q):
COSET = 0x55
@ -27,15 +28,16 @@ def issue_13(reset, clk, d, en, q):
return logic
def test_issue_13():
reset = ResetSignal(0, active=1, isasync=False)
clk = Signal(bool(0))
d = Signal(intbv(0)[32:])
en = Signal(bool(0))
q = Signal(intbv(0)[8:])
clk = Signal(bool(0))
d = Signal(intbv(0)[32:])
en = Signal(bool(0))
q = Signal(intbv(0)[8:])
# toVHDL.numeric_ports = False
issue_13(reset, clk, d, en, q).analyze_convert() == 0
issue_13(reset, clk, d, en, q).analyze_convert() == 0

10
myhdl/test/bugs/test_issue_133.py
View File

@ -1,10 +1,11 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, instance, delay)
@block
def issue_133():
z = Signal(False)
large_signal = Signal(intbv(123456789123456, min=0, max=2**256))
large_signal = Signal(intbv(123456789123456, min=0, max=2 ** 256))
@instance
def check():
z.next = large_signal[10]
@ -13,7 +14,8 @@ def issue_133():
print (large_signal[62:31])
print (large_signal[93:62])
return check
return check
def test_issue_133():
issue_133().verify_convert() == 0

13
myhdl/test/bugs/test_issue_134.py
View File

@ -3,22 +3,26 @@ When an interface signal gets passed into a function, it
can get renamed to the name of the argument. When the
function is called multiple times, this causes name collisions """
import pytest
import myhdl
from myhdl import *
from myhdl import (block, Signal, always_comb)
class AB:
def __init__(self):
self.a = Signal(bool(False))
self.b = Signal(bool(False))
@block
def invert(sigin, sigout):
@always_comb
def foo():
sigout.next = not sigin
return foo
@block
def issue_134(ab_in, ab_out):
""" Instantiate an inverter for each signal """
@ -26,7 +30,8 @@ def issue_134(ab_in, ab_out):
invertb = invert(ab_in.b, ab_out.b)
return inverta, invertb
#@pytest.mark.xfail
# @pytest.mark.xfail
def test_issue_134():
""" check for port name collision"""
assert issue_134(AB(), AB()).analyze_convert() == 0

188
myhdl/test/bugs/test_issue_167.py
View File

@ -9,150 +9,150 @@ from myhdl import Signal, intbv, \
always_comb, instance, \
delay, block, StopSimulation
ASCENDING = True
DESCENDING = False
# modules
@block
def compare(a_1, a_2, z_1, z_2, direction):
""" Combinatorial circuit with two input and two output signals.
Sorting to 'direction'. """
""" Combinatorial circuit with two input and two output signals.
Sorting to 'direction'. """
@always_comb
def logic():
''' Combinatorial logic '''
if direction == (a_1 > a_2):
z_1.next = a_2
z_2.next = a_1
else:
z_1.next = a_1
z_2.next = a_2
@always_comb
def logic():
''' Combinatorial logic '''
if direction == (a_1 > a_2):
z_1.next = a_2
z_2.next = a_1
else:
z_1.next = a_1
z_2.next = a_2
return logic
return logic
@block
def feedthru(in_a, out_z):
""" Equivalent of 'doing nothing'. """
""" Equivalent of 'doing nothing'. """
@always_comb
def logic():
''' Combinatorial logic '''
out_z.next = in_a
@always_comb
def logic():
''' Combinatorial logic '''
out_z.next = in_a
return logic
return logic
@block
def bitonic_merge(list_a, list_z, direction):
""" bitonicMerge:
Generates the output from the input list of signals.
Recursive. """
len_list = len(list_a)
half_len = len_list//2
width = len(list_a[0])
""" bitonicMerge:
Generates the output from the input list of signals.
Recursive. """
len_list = len(list_a)
half_len = len_list // 2
width = len(list_a[0])
if len_list > 1:
tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)]
if len_list > 1:
tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)]
comp = [compare(list_a[i], list_a[i+half_len], tmp[i], tmp[i+half_len], \
direction) for i in range(half_len)]
comp = [compare(list_a[i], list_a[i + half_len], tmp[i], tmp[i + half_len], \
direction) for i in range(half_len)]
lo_merge = bitonic_merge( tmp[:half_len], list_z[:half_len], direction )
hi_merge = bitonic_merge( tmp[half_len:], list_z[half_len:], direction )
lo_merge = bitonic_merge(tmp[:half_len], list_z[:half_len], direction)
hi_merge = bitonic_merge(tmp[half_len:], list_z[half_len:], direction)
return comp, lo_merge, hi_merge
else:
feed = feedthru(list_a[0], list_z[0])
return feed
return comp, lo_merge, hi_merge
else:
feed = feedthru(list_a[0], list_z[0])
return feed
@block
def bitonic_sort(list_a, list_z, direction):
""" bitonicSort:
Produces a bitonic sequence.
Recursive. """
len_list = len(list_a)
half_len = len_list//2
width = len(list_a[0])
""" bitonicSort:
Produces a bitonic sequence.
Recursive. """
len_list = len(list_a)
half_len = len_list // 2
width = len(list_a[0])
if len_list > 1:
tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)]
if len_list > 1:
tmp = [Signal(intbv(0)[width:]) for _ in range(len_list)]
lo_sort = bitonic_sort( list_a[:half_len], tmp[:half_len], ASCENDING )
hi_sort = bitonic_sort( list_a[half_len:], tmp[half_len:], DESCENDING )
merge = bitonic_merge( tmp, list_z, direction )
return lo_sort, hi_sort, merge
else:
feed = feedthru(list_a[0], list_z[0])
return feed
lo_sort = bitonic_sort(list_a[:half_len], tmp[:half_len], ASCENDING)
hi_sort = bitonic_sort(list_a[half_len:], tmp[half_len:], DESCENDING)
merge = bitonic_merge(tmp, list_z, direction)
return lo_sort, hi_sort, merge
else:
feed = feedthru(list_a[0], list_z[0])
return feed
# tests
@block
def array8sorter(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7):
''' Sort Array with 8 values '''
''' Sort Array with 8 values '''
list_a = [a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7]
list_z = [z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7]
list_a = [a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7]
list_z = [z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7]
sort = bitonic_sort(list_a, list_z, ASCENDING)
return sort
sort = bitonic_sort(list_a, list_z, ASCENDING)
return sort
class TestBitonicSort(unittest.TestCase):
''' Test class for bitonic sort '''
''' Test class for bitonic sort '''
def test_sort(self):
""" Check the functionality of the bitonic sort """
length = 8
width = 4
def test_sort(self):
""" Check the functionality of the bitonic sort """
length = 8
width = 4
@block
def test_impl():
''' test implementation '''
inputs = [ Signal(intbv(0)[width:]) for _ in range(length) ]
outputs = [ Signal(intbv(0)[width:]) for _ in range(length) ]
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7 = outputs
a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7 = inputs
@block
def test_impl():
''' test implementation '''
inputs = [ Signal(intbv(0)[width:]) for _ in range(length) ]
outputs = [ Signal(intbv(0)[width:]) for _ in range(length) ]
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7 = outputs
a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7 = inputs
inst = array8sorter(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7)
inst = array8sorter(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
z_0, z_1, z_2, z_3, z_4, z_5, z_6, z_7)
@instance
def check():
''' testbench input and validation '''
for i in range(100):
data = [randrange(2**width) for i in range(length)]
for i in range(length):
inputs[i].next = data[i]
yield delay(10)
data.sort()
self.assertEqual(data, outputs, 'wrong data')
raise StopSimulation
@instance
def check():
''' testbench input and validation '''
for i in range(100):
data = [randrange(2 ** width) for i in range(length)]
for i in range(length):
inputs[i].next = data[i]
yield delay(10)
data.sort()
self.assertEqual(data, outputs, 'wrong data')
raise StopSimulation
return inst, check
inst = test_impl()
inst.run_sim()
return inst, check
inst = test_impl()
inst.run_sim()
# convert
def test_issue_167():
''' Convert to VHDL '''
length = 8
width = 4
sigs = [Signal(intbv(0)[width:]) for _ in range(2*length)]
inst = array8sorter( *sigs )
inst.convert( hdl='VHDL' )
def test_issue_167():
''' Convert to VHDL '''
length = 8
width = 4
sigs = [Signal(intbv(0)[width:]) for _ in range(2 * length)]
inst = array8sorter(*sigs)
inst.convert(hdl='VHDL')
if __name__ == '__main__':
test_issue_167()
test_issue_167()

13
myhdl/test/bugs/test_issue_169.py
View File

@ -1,15 +1,14 @@
from myhdl import Signal, block, delay, instance
import pytest
class MyTest1:
def __init__(self):
self.clock = Signal(bool(0))
@block
def test(self):
@instance
def func():
i = 0
@ -22,12 +21,13 @@ class MyTest1:
class MyTest2:
def __init__(self):
self.clock = Signal(bool(1))
@block
def test(self):
@instance
def func():
i = 0
@ -43,14 +43,15 @@ class MyTest2:
def mytest_bench():
inst1 = MyTest1()
inst2 = MyTest2()
# Two instances are created
ins1 = inst1.test()
ins2 = inst2.test()
return ins1, ins2
#@pytest.mark.xfail
# @pytest.mark.xfail
def test_issue_169():
test_inst = mytest_bench()
test_inst.verify_convert()

13
myhdl/test/bugs/test_issue_18.py
View File

@ -1,17 +1,17 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, always, always_comb, toVHDL)
@block
def issue_18(dout, din, addr, we, clk, depth=128):
""" Ram model """
mem = [Signal(intbv(0)[8:]) for i in range(depth)]
mem = [Signal(intbv(0)[8:]) for __ in range(depth)]
@always(clk.posedge)
def write():
if we:
mem[addr].next = din
@always_comb
def read():
dout.next = mem[addr]
@ -26,6 +26,7 @@ addr = Signal(intbv(0)[7:])
we = Signal(bool(0))
clk = Signal(bool(0))
def test_issue_18():
toVHDL.std_logic_ports = True
assert issue_18(dout, din, addr, we, clk).analyze_convert() == 0

8
myhdl/test/bugs/test_issue_185.py
View File

@ -1,12 +1,14 @@
from myhdl import *
from myhdl import (block, Signal, intbv, ResetSignal, always_seq)
def shift_left(c, a, b):
c.next = a << b
@block
def shifter(reset, clock, opa, opb, result):
@always_seq(clock.posedge, reset = reset)
@always_seq(clock.posedge, reset=reset)
def assign():
shift_left(result, opa, opb)

6
myhdl/test/bugs/test_issue_40.py
View File

@ -1,7 +1,5 @@
#! /usr/bin/env python
from myhdl import (block, Signal, intbv, always_seq, instances, ResetSignal)
import myhdl
from myhdl import *
@block
def mpegChannel(clk, rst):
@ -23,11 +21,9 @@ def mpegChannel(clk, rst):
return instances()
def test_issue_40():
clk = Signal(bool(0))
rst = ResetSignal(0, active=1, isasync=True)
assert mpegChannel(clk, rst).analyze_convert() == 0

12
myhdl/test/bugs/test_issue_9.py
View File

@ -1,14 +1,14 @@
import myhdl
from myhdl import *
from myhdl import (Signal, enum)
def issue_9():
t_State = enum('foo', 'bar')
assert (Signal(t_State.foo) == Signal(t_State.bar)) == False
assert (Signal(t_State.foo) != Signal(t_State.bar)) == True
assert (Signal(t_State.foo) == Signal(t_State.foo)) == True
assert (Signal(t_State.foo) != Signal(t_State.foo)) == False
assert (Signal(t_State.foo) == Signal(t_State.bar)) == False
assert (Signal(t_State.foo) != Signal(t_State.bar)) == True
assert (Signal(t_State.foo) == Signal(t_State.foo)) == True
assert (Signal(t_State.foo) != Signal(t_State.foo)) == False
def test_issue_9():

38
myhdl/test/bugs/test_issue_98.py
View File

@ -1,38 +1,42 @@
import myhdl
from myhdl import *
#from myhdl.conversion import analyze
from myhdl import (block, Signal, intbv, always_comb, TristateSignal, toVHDL, toVerilog)
import pytest
@block
def issue_98(sda, scl, sda_i, sda_o, scl_i, scl_o):
sda_d, scl_d = sda.driver(), scl.driver()
@always_comb
def hdl():
sda_i.next = sda
sda_d.next = 0 if not sda_o else None
scl_i.next = scl
scl_d.next = None if not scl_o else 1
return hdl
sda_d, scl_d = sda.driver(), scl.driver()
@always_comb
def hdl():
sda_i.next = sda
sda_d.next = 0 if not sda_o else None
scl_i.next = scl
scl_d.next = None if not scl_o else 1
return hdl
@pytest.mark.xfail
def test_issue_98_1():
sda_i, sda_o, scl_i, scl_o = [Signal(False) for i in range(4)]
sda, scl = [TristateSignal(False) for i in range(2)]
sda_i, sda_o, scl_i, scl_o = [Signal(False) for __ in range(4)]
sda, scl = [TristateSignal(False) for __ in range(2)]
toVHDL.name = toVerilog.name = 'issue_98_1'
assert issue_98(sda, scl, sda_i, sda_o, scl_i, scl_o).analyze_convert() == 0
@pytest.mark.xfail
def test_issue_98_2():
sda_i, sda_o, scl_i, scl_o = [Signal(intbv(0)[2:0]) for i in range(4)]
sda, scl = [TristateSignal(intbv(0)[2:0]) for i in range(2)]
sda_i, sda_o, scl_i, scl_o = [Signal(intbv(0)[2:0]) for __ in range(4)]
sda, scl = [TristateSignal(intbv(0)[2:0]) for __ in range(2)]
toVHDL.name = toVerilog.name = 'issue_98_2'
assert issue_98(sda, scl, sda_i, sda_o, scl_i, scl_o).analyze_convert() == 0
@pytest.mark.xfail
def test_issue_98_3():
sda_i, sda_o, scl_i, scl_o = [Signal(intbv(0)[1:0]) for i in range(4)]
sda, scl = [TristateSignal(intbv(0)[1:0]) for i in range(2)]
sda_i, sda_o, scl_i, scl_o = [Signal(intbv(0)[1:0]) for __ in range(4)]
sda, scl = [TristateSignal(intbv(0)[1:0]) for __ in range(2)]
toVHDL.name = toVerilog.name = 'issue_98_3'
assert issue_98(sda, scl, sda_i, sda_o, scl_i, scl_o).analyze_convert() == 0

5
myhdl/test/conversion/general/test_ShadowSignal.py
View File

@ -141,12 +141,13 @@ def bench_ConcatSignalWithConsts():
def test_ConcatSignalWithConsts():
assert conversion.verify(bench_ConcatSignalWithConsts()) == 0
@block
def bench_ConcatSignalUndriven():
n_sigs = 32
sig_list = [Signal(False) for n in range(n_sigs)]
sig_list = [Signal(False) for __ in range(n_sigs)]
concat_sig = ConcatSignal(*reversed(sig_list))
@instance
@ -157,9 +158,11 @@ def bench_ConcatSignalUndriven():
return check
def test_ConcatSignalUndriven():
assert conversion.verify(bench_ConcatSignalUndriven()) == 0
@block
def bench_TristateSignal():
s = TristateSignal(intbv(0)[8:])

11
myhdl/test/conversion/general/test_adapter.py
View File

@ -1,5 +1,6 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, instance, delay,
ConcatSignal, always_comb)
@block
def adapter(o_err, i_err, o_spec, i_spec):
@ -38,7 +39,7 @@ def adapter(o_err, i_err, o_spec, i_spec):
@block
def bench_adapter(hdl=None):
o_spec = ('c', 'a', 'other', 'nomatch')
i_spec = { 'a' : 1, 'b' : 2, 'c' : 0, 'd' : 3, 'e' : 4, 'f' : 5, }
i_spec = { 'a': 1, 'b': 2, 'c': 0, 'd': 3, 'e': 4, 'f': 5, }
o_err = Signal(intbv(0)[4:])
i_err = Signal(intbv(0)[6:])
@ -48,7 +49,8 @@ def bench_adapter(hdl=None):
else:
dut = adapter(o_err, i_err, o_spec, i_spec)
N = 2**len(i_err)
N = 2 ** len(i_err)
@instance
def stimulus():
for i in range(N):
@ -62,6 +64,7 @@ def bench_adapter(hdl=None):
return dut, stimulus
def test_adapter():
assert bench_adapter().verify_convert() == 0

23
myhdl/test/conversion/general/test_bin2gray.py
View File

@ -3,6 +3,7 @@ path = os.path
from myhdl import block, Signal, intbv, delay, instance, always_comb
@block
def bin2gray2(B, G, width):
""" Gray encoder.
@ -11,16 +12,19 @@ def bin2gray2(B, G, width):
G -- output intbv signal, gray encoded
width -- bit width
"""
@instance
def logic():
Bext = intbv(0)[width+1:]
Bext = intbv(0)[width + 1:]
while 1:
yield B
Bext[:] = B
for i in range(width):
G.next[i] = Bext[i+1] ^ Bext[i]
G.next[i] = Bext[i + 1] ^ Bext[i]
return logic
@block
def bin2gray(B, G, width):
@ -34,10 +38,10 @@ def bin2gray(B, G, width):
@always_comb
def logic():
Bext = intbv(0)[width+1:]
Bext = intbv(0)[width + 1:]
Bext[:] = B
for i in range(width):
G.next[i] = Bext[i+1] ^ Bext[i]
G.next[i] = Bext[i + 1] ^ Bext[i]
return logic
@ -50,23 +54,24 @@ def bin2grayBench(width, bin2gray):
bin2gray_inst = bin2gray(B, G, width)
n = 2**width
n = 2 ** width
@instance
def stimulus():
for i in range(n):
B.next = i
yield delay(10)
#print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
#print bin(G, width)
#print bin(G_v, width)
# print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
# print bin(G, width)
# print bin(G_v, width)
print("%d" % G)
return stimulus, bin2gray_inst
def test1():
assert bin2grayBench(width=8, bin2gray=bin2gray).verify_convert() == 0
assert bin2grayBench(width=8, bin2gray=bin2gray).verify_convert() == 0
def test2():
assert bin2grayBench(width=8, bin2gray=bin2gray2).verify_convert() == 0

152
myhdl/test/conversion/general/test_binops.py
View File

@ -1,4 +1,5 @@
from myhdl import *
from myhdl import (block, Signal, intbv, modbv, delay, always_comb, instance, instances, StopSimulation)
@block
def binOpsCheck0(
@ -9,15 +10,16 @@ def binOpsCheck0(
y,
z,
):
@always_comb
def outputs():
x.next = a
x.next = a
y.next = a | b
z.next = a | b | c
return instances()
@block
def binOpsCheck1(
a,
@ -25,44 +27,46 @@ def binOpsCheck1(
y,
z,
):
@always_comb
def outputs():
x.next = a[0]
x.next = a[0]
y.next = a[0] | a[1]
z.next = a[0] | a[1] | a[2]
return instances()
@block
def binOpsCheck2(
a,
z,
):
@always_comb
def outputs():
z[0].next = a[0]
z[0].next = a[0]
z[1].next = a[0] | a[1]
z[2].next = a[0] | a[1] | a[2]
return instances()
@block
def binOpsCheckBench0():
clk = Signal(bool(0))
a = Signal(modbv(0)[1:])
b = Signal(modbv(0)[1:])
c = Signal(modbv(0)[1:])
x = Signal(modbv(0)[1:])
y = Signal(modbv(0)[1:])
z = Signal(modbv(0)[1:])
clk = Signal(bool(0))
a = Signal(modbv(0)[1:])
b = Signal(modbv(0)[1:])
c = Signal(modbv(0)[1:])
x = Signal(modbv(0)[1:])
y = Signal(modbv(0)[1:])
z = Signal(modbv(0)[1:])
@instance
def clkgen():
clk.next = 1
for i in range(400):
for dummy in range(400):
yield delay(10)
clk.next = not clk
@ -153,30 +157,30 @@ def binOpsCheckBench0():
assert y == 0x0
assert z == 0x0
yield clk.posedge
i_binOpsCheck = binOpsCheck0(a, b, c, x, y, z)
return instances()
@block
def binOpsCheckBench1():
clk = Signal(bool(0))
a = Signal(modbv(0)[1:])
b = Signal(modbv(0)[1:])
c = Signal(modbv(0)[1:])
x = Signal(False)
y = Signal(False)
z = Signal(False)
clk = Signal(bool(0))
a = Signal(modbv(0)[1:])
b = Signal(modbv(0)[1:])
c = Signal(modbv(0)[1:])
x = Signal(False)
y = Signal(False)
z = Signal(False)
@instance
def clkgen():
clk.next = 1
for i in range(400):
for dummy in range(400):
yield delay(10)
clk.next = not clk
@instance
def stimulus():
a.next = 0x0
@ -264,30 +268,30 @@ def binOpsCheckBench1():
assert y == 0x0
assert z == 0x0
yield clk.posedge
i_binOpsCheck = binOpsCheck0(a, b, c, x, y, z)
return instances()
@block
def binOpsCheckBench2():
clk = Signal(bool(0))
a = Signal(modbv(0)[2:])
b = Signal(modbv(0)[2:])
c = Signal(modbv(0)[2:])
x = Signal(modbv(0)[2:])
y = Signal(modbv(0)[2:])
z = Signal(modbv(0)[2:])
clk = Signal(bool(0))
a = Signal(modbv(0)[2:])
b = Signal(modbv(0)[2:])
c = Signal(modbv(0)[2:])
x = Signal(modbv(0)[2:])
y = Signal(modbv(0)[2:])
z = Signal(modbv(0)[2:])
@instance
def clkgen():
clk.next = 1
for i in range(400):
for dummy in range(400):
yield delay(10)
clk.next = not clk
@instance
def stimulus():
a.next = 0x0
@ -375,9 +379,8 @@ def binOpsCheckBench2():
assert y == 0x0
assert z == 0x0
yield clk.posedge
i_binOpsCheck = binOpsCheck0(a, b, c, x, y, z)
i_binOpsCheck = binOpsCheck0(a, b, c, x, y, z)
return instances()
@ -386,65 +389,74 @@ def test_binOps0():
sim = binOpsCheckBench0()
sim.run_sim()
def test_binOps0_convert():
i_dut = binOpsCheckBench0()
assert i_dut.analyze_convert() == 0
#assert i_dut.verify_simulator() == 0
#assert i_dut.verify_convert() == 0
# assert i_dut.verify_simulator() == 0
# assert i_dut.verify_convert() == 0
def test_binOps1():
sim = binOpsCheckBench1()
sim.run_sim()
def test_binOps1_convert():
i_dut = binOpsCheckBench1()
assert i_dut.analyze_convert() == 0
#assert i_dut.verify_simulator() == 0
# assert i_dut.verify_simulator() == 0
def test_binOps1b_convert():
a = Signal(modbv(0)[1:])
b = Signal(modbv(0)[1:])
c = Signal(modbv(0)[1:])
x = Signal(False)
y = Signal(False)
z = Signal(False)
a = Signal(modbv(0)[1:])
b = Signal(modbv(0)[1:])
c = Signal(modbv(0)[1:])
x = Signal(False)
y = Signal(False)
z = Signal(False)
i_dut = binOpsCheck0(a, b, c, x, y, z)
assert i_dut.analyze_convert() == 0
def test_binOps1c_convert():
a = Signal(intbv(0)[1:])
b = Signal(intbv(0)[1:])
c = Signal(intbv(0)[1:])
x = Signal(False)
y = Signal(False)
z = Signal(False)
a = Signal(intbv(0)[1:])
b = Signal(intbv(0)[1:])
c = Signal(intbv(0)[1:])
x = Signal(False)
y = Signal(False)
z = Signal(False)
i_dut = binOpsCheck0(a, b, c, x, y, z)
assert i_dut.analyze_convert() == 0
def test_binOps1d_convert():
a = Signal(intbv(0)[3:])
x = Signal(False)
y = Signal(False)
z = Signal(False)
a = Signal(intbv(0)[3:])
x = Signal(False)
y = Signal(False)
z = Signal(False)
i_dut = binOpsCheck1(a, x, y, z)
assert i_dut.analyze_convert() == 0
def test_binOps1e_convert():
a = Signal(intbv(0)[3:])
z = Signal(intbv(0)[3:])
a = Signal(intbv(0)[3:])
z = Signal(intbv(0)[3:])
i_dut = binOpsCheck2(a, z)
assert i_dut.analyze_convert() == 0
def test_binOps2():
sim = binOpsCheckBench2()
sim.run_sim()
def test_binOps2_convert():
i_dut = binOpsCheckBench2()
assert i_dut.analyze_convert() == 0
#assert i_dut.verify_convert() == 0
#assert i_dut.verify_simulator() == 0
# assert i_dut.verify_convert() == 0
# assert i_dut.verify_simulator() == 0

17
myhdl/test/conversion/general/test_case.py
View File

@ -1,5 +1,5 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always_comb, instance)
@block
def map_case4(z, a):
@ -17,6 +17,7 @@ def map_case4(z, a):
return logic
@block
def map_case2(z, a):
@ -30,6 +31,7 @@ def map_case2(z, a):
return logic
@block
def map_case3(z, a):
@ -44,6 +46,7 @@ def map_case3(z, a):
return logic
@block
def map_case4_full(z, a):
@ -78,6 +81,7 @@ def bench_case(map_case, N):
return stimulus, inst
@block
def bool_bench_case(map_case):
@ -95,6 +99,7 @@ def bool_bench_case(map_case):
return stimulus, inst
@block
def length1_bench_case(map_case):
@ -112,26 +117,34 @@ def length1_bench_case(map_case):
return stimulus, inst
def test_case4():
assert bench_case(map_case4, 4).verify_convert() == 0
def test_case2():
assert bench_case(map_case2, 2).verify_convert() == 0
def test_case3():
assert bench_case(map_case3, 3).verify_convert() == 0
def test_case4_full():
assert bench_case(map_case4_full, 4).verify_convert() == 0
def test_case2_bool():
assert bool_bench_case(map_case3).verify_convert() == 0
def test_case3_bool():
assert bool_bench_case(map_case3).verify_convert() == 0
def test_case2_single_bit():
assert length1_bench_case(map_case3).verify_convert() == 0
def test_case3_single_bit():
assert length1_bench_case(map_case3).verify_convert() == 0

32
myhdl/test/conversion/general/test_class_defined_signals.py
View File

@ -1,4 +1,6 @@
from myhdl import *
from myhdl import (block, Signal, delay, always, always_comb,
instance, StopSimulation, conversion)
class HDLClass(object):
@ -20,6 +22,7 @@ class HDLClass(object):
return do_something, assignments
class InterfaceWithInstanceSignal(object):
def __init__(self):
@ -64,6 +67,7 @@ def different_class_pipeline(clock, input_interface, output_interface):
return class_hdl_inst1, class_hdl_inst2
@block
def common_class_pipeline(clock, input_interface, output_interface):
@ -87,6 +91,7 @@ def common_class_pipeline(clock, input_interface, output_interface):
return class_hdl_inst1, class_hdl_inst2, class_hdl_inst3, class_hdl_inst4
@block
def interface_with_method_pipeline(clock, input_interface, output_interface):
@ -110,11 +115,11 @@ def interface_with_method_pipeline(clock, input_interface, output_interface):
return class_hdl_inst1, class_hdl_inst2, class_hdl_inst3, class_hdl_inst4
@block
def bench(class_name='different_class'):
clk = Signal(False)
reset = Signal(False)
input_interface = Signal(False)
output_interface = Signal(False)
@ -124,7 +129,7 @@ def bench(class_name='different_class'):
def clkgen():
clk.next = 0
for n in range(N):
for dummy in range(N):
yield delay(10)
clk.next = not clk
@ -144,30 +149,15 @@ def bench(class_name='different_class'):
return pipeline_inst, clkgen
def test_multiple_class_single_method():
clock = Signal(False)
reset = Signal(False)
input_interface = Signal(False)
output_interface = Signal(False)
assert conversion.verify(bench()) == 0
def test_single_class_single_method():
clock = Signal(False)
reset = Signal(False)
input_interface = Signal(False)
output_interface = Signal(False)
assert conversion.verify(bench(class_name='common_class')) == 0
def test_single_interface_with_single_method():
clock = Signal(False)
reset = Signal(False)
input_interface = Signal(False)
output_interface = Signal(False)
assert conversion.verify(bench(class_name='interface')) == 0

25
myhdl/test/conversion/general/test_colon_plus_operator.py
View File

@ -1,4 +1,8 @@
from myhdl import *
from myhdl import (block, Signal, intbv, modbv, delay, always_seq,
ResetSignal, instance, instances, StopSimulation,
# conversion)
)
@block
def chunk_buffer(Clk, Reset, Input, Output):
@ -12,13 +16,15 @@ def chunk_buffer(Clk, Reset, Input, Output):
return instances()
@block
def chunk_buffer_sim(Clk, Reset, Input, Output):
chunk_buffer0 = chunk_buffer(Clk, Reset, Input, Output)
dut = chunk_buffer(Clk, Reset, Input, Output)
tCK = 20
tReset = int(tCK * 3.5)
@instance
def tb_clk():
Clk.next = False
@ -34,21 +40,24 @@ def chunk_buffer_sim(Clk, Reset, Input, Output):
Reset.next = 0
Input.next = 0xABCDEF
for i in range(100):
for dummy in range(100):
yield delay(int(tCK // 2))
raise StopSimulation
return instances()
def test_top_level_interfaces_verify():
Clk = Signal(bool(0))
Reset = ResetSignal(0, 1, True)
Input = Signal(intbv(0)[256:])
Output = Signal(intbv(0)[8:])
top_sim = chunk_buffer_sim(Clk, Reset, Input, Output)
assert conversion.analyze(top_sim) == 0
# assert conversion.analyze(top_sim) == 0
# as top_sim is a Block object, let's use the proper method
assert top_sim.analyze_convert() == 0
top = chunk_buffer(Clk, Reset, Input, Output)
top.name = 'ChunkBuffer'

9
myhdl/test/conversion/general/test_constants.py
View File

@ -1,5 +1,5 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, always_comb)
@block
def constants(v, u, x, y, z, a):
@ -20,9 +20,10 @@ def constants(v, u, x, y, z, a):
return logic
x, y, z, a = [Signal(bool(0)) for i in range(4)]
x, y, z, a = [Signal(bool(0)) for i in range(4)]
u = Signal(intbv(0)[8:])
v = Signal(intbv(0, min=-3, max=9))
def test_constants():
assert constants(v, u, x, y, z, a).analyze_convert() == 0
assert constants(v, u, x, y, z, a).analyze_convert() == 0

16
myhdl/test/conversion/general/test_convert_deprecation.py
View File

@ -1,6 +1,10 @@
from myhdl import *
from myhdl import (Signal, intbv, always_comb, conversion, toVHDL, toVerilog)
from myhdl._Simulation import Simulation
from myhdl._traceSignals import traceSignals
import pytest
def bin2gray_depr(B, G, width):
""" Gray encoder.
@ -13,33 +17,39 @@ def bin2gray_depr(B, G, width):
@always_comb
def logic():
Bext = intbv(0)[width+1:]
Bext = intbv(0)[width + 1:]
Bext[:] = B
for i in range(width):
G.next[i] = Bext[i+1] ^ Bext[i]
G.next[i] = Bext[i + 1] ^ Bext[i]
return logic
width = 1
BB = Signal(intbv(0)[width:])
GG = Signal(intbv(0)[width:])
def testOldVerify():
with pytest.deprecated_call():
conversion.verify(bin2gray_depr, width, BB, GG)
def testOldAnalyze():
with pytest.deprecated_call():
conversion.analyze(bin2gray_depr, width, BB, GG)
def testOldToVHDL():
with pytest.deprecated_call():
toVHDL(bin2gray_depr, width, BB, GG)
def testOldToVerilog():
with pytest.deprecated_call():
toVerilog(bin2gray_depr, width, BB, GG)
def testOldToTraceSignals():
with pytest.deprecated_call():
vcd = traceSignals(bin2gray_depr, width, BB, GG)

12
myhdl/test/conversion/general/test_dec.py
View File

@ -4,8 +4,7 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always, instance, StopSimulation)
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@ -89,7 +88,7 @@ def decFunc(count, enable, clock, reset, n):
@block
def decTask(count, enable, clock, reset, n):
def decTaskFunc(cnt, enable, reset, n):
def decTaskFunc(cnt, enable, n):
if enable:
if cnt == -n:
cnt[:] = n - 1
@ -106,7 +105,7 @@ def decTask(count, enable, clock, reset, n):
count.next = 0
else:
# print count
decTaskFunc(cnt, enable, reset, n)
decTaskFunc(cnt, enable, n)
count.next = cnt
return decTaskGen
@ -127,7 +126,7 @@ def decTaskFreeVar(count, enable, clock, reset, n):
while 1:
yield clock.posedge, reset.negedge
if reset == ACTIVE_LOW:
count.next = 0
count.next = 0
else:
# print count
decTaskFunc()
@ -142,9 +141,8 @@ def DecBench(dec):
n = 2 ** (m - 1)
count = Signal(intbv(0, min=-n, max=n))
count_v = Signal(intbv(0, min=-n, max=n))
enable = Signal(bool(0))
clock, reset = [Signal(bool(1)) for i in range(2)]
clock, reset = [Signal(bool(1)) for __ in range(2)]
@instance
def clockGen():

15
myhdl/test/conversion/general/test_errors.py
View File

@ -1,5 +1,5 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, modbv, always)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
from myhdl.conversion import verify
@ -7,11 +7,14 @@ from myhdl.conversion import verify
@block
def sigAugmAssignUnsupported(z, a):
@always(a)
def logic():
z.next += a
return logic
def test_SigAugmAssignUnsupported():
z = Signal(intbv(0)[8:])
a = Signal(intbv(0)[8:])
@ -22,15 +25,19 @@ def test_SigAugmAssignUnsupported():
else:
assert False
@block
def modbvRange(z, a, b):
@always(a, b)
def logic():
s = modbv(0, min=0, max=35)
s[:] = a + b
z.next = s
return logic
def test_modbvRange():
z = Signal(intbv(0)[8:])
a = Signal(intbv(0)[4:])
@ -42,13 +49,17 @@ def test_modbvRange():
else:
assert False
@block
def modbvSigRange(z, a, b):
@always(a, b)
def logic():
z.next = a + b
return logic
def test_modbvSigRange():
z = Signal(modbv(0, min=0, max=42))
a = Signal(intbv(0)[4:])

17
myhdl/test/conversion/general/test_fsm.py
View File

@ -1,8 +1,7 @@
import os
path = os.path
import myhdl
from myhdl import *
from myhdl import (block, Signal, enum, intbv, delay, always, instance, StopSimulation)
# SEARCH, CONFIRM, SYNC = range(3)
ACTIVE_LOW = bool(0)
@ -11,6 +10,7 @@ t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC')
t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold")
@block
def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
@ -24,7 +24,7 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
"""
index = Signal(intbv(0)[8:]) # position in frame
index = Signal(intbv(0)[8:]) # position in frame
@always(clk.posedge, reset_n.negedge)
def FSM():
@ -49,22 +49,21 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
if index == 0:
if not syncFlag:
state.next = t_State.SEARCH
SOF.next = (index == FRAME_SIZE-1)
SOF.next = (index == FRAME_SIZE - 1)
else:
raise ValueError("Undefined state")
return FSM
@block
def FSMBench(FramerCtrl, t_State):
SOF = Signal(bool(0))
SOF_v = Signal(bool(0))
syncFlag = Signal(bool(0))
clk = Signal(bool(0))
reset_n = Signal(bool(1))
state = Signal(t_State.SEARCH)
state_v = Signal(intbv(0)[8:])
framerctrl_inst = FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State)
@ -77,7 +76,7 @@ def FSMBench(FramerCtrl, t_State):
yield delay(10)
reset_n.next = 1
yield delay(10)
for i in range(1000):
for dummy in range(1000):
yield delay(10)
clk.next = not clk
@ -92,7 +91,7 @@ def FSMBench(FramerCtrl, t_State):
syncFlag.next = 1
yield clk.posedge
syncFlag.next = 0
for j in range(n-1):
for dummy in range(n - 1):
yield clk.posedge
raise StopSimulation
@ -105,7 +104,7 @@ def FSMBench(FramerCtrl, t_State):
# in the end, this should work
# print state
return framerctrl_inst, clkgen, stimulus, check
return framerctrl_inst, clkgen, stimulus, check
def test():

50
myhdl/test/conversion/general/test_hec.py
View File

@ -2,11 +2,12 @@ import os
path = os.path
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, concat, instance, downrange,)
# from .util import setupCosimulation # not found!
COSET = 0x55
def calculateHecRef(header):
""" Return hec for an ATM header.
@ -22,6 +23,7 @@ def calculateHecRef(header):
)
return hec ^ COSET
def calculateHecFunc(header):
""" Return hec for an ATM header.
@ -39,6 +41,7 @@ def calculateHecFunc(header):
h ^= COSET
return h
def calculateHecTask(hec, header):
""" Calculate hec for an ATM header.
@ -56,12 +59,14 @@ def calculateHecTask(hec, header):
h ^= COSET
hec[:] = h
@block
def HecCalculatorPlain(hec, header):
""" Hec calculation module.
Plain version.
"""
@instance
def logic():
h = intbv(0)[8:]
@ -76,18 +81,20 @@ def HecCalculatorPlain(hec, header):
bit ^ h[7]
)
hec.next = h ^ COSET
return logic
def HecCalculatorFunc(hec, header):
""" Hec calculation module.
Version with function call.
"""
h = intbv(0)[8:]
while 1:
yield header
hec.next = calculateHecFunc(header=header)
def HecCalculatorTask(hec, header):
""" Hec calculation module.
@ -99,6 +106,7 @@ def HecCalculatorTask(hec, header):
calculateHecTask(h, header)
hec.next = h
def HecCalculatorTask2(hec, header):
""" Hec calculation module.
@ -110,10 +118,9 @@ def HecCalculatorTask2(hec, header):
calculateHecTask(header=header, hec=h)
hec.next = h
def HecCalculator_v(name, hec, header):
return setupCosimulation(**locals())
#
# def HecCalculator_v(name, hec, header):
# return setupCosimulation(**locals())
headers = [ 0x00000000,
@ -121,14 +128,14 @@ headers = [ 0x00000000,
0xbac6f4ca
]
headers.extend([randrange(2**32-1) for i in range(10)])
headers.extend([randrange(2 ** 32 - 1) for i in range(10)])
headers = tuple(headers)
@block
def HecBench(HecCalculator):
hec = Signal(intbv(0)[8:])
hec_v = Signal(intbv(0)[8:])
header = Signal(intbv(-1)[32:])
heccalc_inst = HecCalculator(hec, header)
@ -142,21 +149,22 @@ def HecBench(HecCalculator):
return stimulus, heccalc_inst
## def testPlain(self):
## sim = self.bench(HecCalculatorPlain)
## Simulation(sim).run()
# # def testPlain(self):
# # sim = self.bench(HecCalculatorPlain)
# # Simulation(sim).run()
## def testFunc(self):
## sim = self.bench(HecCalculatorFunc)
## Simulation(sim).run()
# # def testFunc(self):
# # sim = self.bench(HecCalculatorFunc)
# # Simulation(sim).run()
## def testTask(self):
## sim = self.bench(HecCalculatorTask)
## Simulation(sim).run()
# # def testTask(self):
# # sim = self.bench(HecCalculatorTask)
# # Simulation(sim).run()
# # def testTask2(self):
# # sim = self.bench(HecCalculatorTask2)
# # Simulation(sim).run()
## def testTask2(self):
## sim = self.bench(HecCalculatorTask2)
## Simulation(sim).run()
def testPlain():
assert HecBench(HecCalculatorPlain).verify_convert() == 0

66
myhdl/test/conversion/general/test_inc.py
View File

@ -1,17 +1,16 @@
import sys
import os
path = os.path
import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always, instance)
from myhdl.conversion import verify
ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1)
@block
def incRef(count, enable, clock, reset, n):
""" Incrementer with enable.
@ -22,6 +21,7 @@ def incRef(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@instance
def logic():
while 1:
@ -31,11 +31,13 @@ def incRef(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@block
def inc(count, enable, clock, reset, n):
""" Incrementer with enable.
count -- output
@ -45,7 +47,7 @@ def inc(count, enable, clock, reset, n):
n -- counter max value
"""
@always(clock.posedge, reset.negedge)
def incProcess():
if reset == 0:
@ -53,27 +55,30 @@ def inc(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return incProcess
@block
def inc2(count, enable, clock, reset, n):
@always(clock.posedge, reset.negedge)
def incProcess():
if reset == ACTIVE_LOW:
count.next = 0
else:
if enable:
if count == n-1:
if count == n - 1:
count.next = 0
else:
count.next = count + 1
return incProcess
@block
def incFunc(count, enable, clock, reset, n):
def incFuncFunc(cnt, enable):
count_next = intbv(0, min=0, max=n)
count_next[:] = cnt
@ -89,12 +94,12 @@ def incFunc(count, enable, clock, reset, n):
count.next = incFuncFunc(count, enable)
return incFuncGen
@block
def incTask(count, enable, clock, reset, n):
def incTaskFunc(cnt, enable, reset, n):
def incTaskFunc(cnt, enable, n):
if enable:
cnt[:] = (cnt + 1) % n
@ -108,7 +113,7 @@ def incTask(count, enable, clock, reset, n):
count.next = 0
else:
# print count
incTaskFunc(cnt, enable, reset, n)
incTaskFunc(cnt, enable, n)
count.next = cnt
return incTaskGen
@ -116,7 +121,7 @@ def incTask(count, enable, clock, reset, n):
@block
def incTaskFreeVar(count, enable, clock, reset, n):
def incTaskFunc():
if enable:
count.next = (count + 1) % n
@ -124,7 +129,7 @@ def incTaskFreeVar(count, enable, clock, reset, n):
@always(clock.posedge, reset.negedge)
def incTaskGen():
if reset == ACTIVE_LOW:
count.next = 0
count.next = 0
else:
# print count
incTaskFunc()
@ -136,22 +141,20 @@ def incTaskFreeVar(count, enable, clock, reset, n):
def IncBench(inc):
NR_CYCLES = 201
m = 8
n = 2 ** m
count = Signal(intbv(0)[m:])
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool(0)) for i in range(2)]
clock, reset = [Signal(bool(0)) for __ in range(2)]
inc_inst = inc(count, enable, clock, reset, n=n)
@instance
def clockgen():
clock.next = 1
for i in range(NR_CYCLES):
for dummy in range(NR_CYCLES):
yield delay(10)
clock.next = not clock
@ -169,19 +172,22 @@ def IncBench(inc):
return inc_inst, clockgen, monitor
def test_incReg():
def test_incReg():
assert verify(IncBench(incRef)) == 0
def test_inc():
def test_inc():
assert verify(IncBench(inc)) == 0
def test_inc2():
def test_inc2():
assert verify(IncBench(inc2)) == 0
def testIncTask():
assert verify(IncBench(incTask)) == 0
def testIncFunc():
assert verify(IncBench(incFunc)) == 0

100
myhdl/test/conversion/general/test_initial_values.py
View File

@ -1,7 +1,9 @@
from random import randrange
from myhdl import *
import myhdl
from myhdl import (block, Signal, enum, intbv, modbv, delay, always_comb, always_seq,
always, instance, instances, StopSimulation, toVHDL, toVerilog,
ResetSignal, conversion)
@block
def initial_value_enum_bench(initial_val, **kwargs):
@ -20,7 +22,7 @@ def initial_value_enum_bench(initial_val, **kwargs):
def clkgen():
clk.next = 0
for n in range(N):
for dummy in range(N):
yield delay(10)
clk.next = not clk
@ -46,6 +48,7 @@ def initial_value_enum_bench(initial_val, **kwargs):
return state_walker, clkgen
@block
def bool_writer(signal, clk):
@ -55,6 +58,7 @@ def bool_writer(signal, clk):
return writer
@block
def int_writer(signal, clk):
@ -64,6 +68,7 @@ def int_writer(signal, clk):
return writer
@block
def initial_value_bench(initial_val, **kwargs):
@ -102,7 +107,7 @@ def initial_value_bench(initial_val, **kwargs):
def clkgen():
clk.next = 0
for n in range(N):
for dummy in range(N):
yield delay(10)
clk.next = not clk
@ -130,9 +135,9 @@ def initial_value_bench(initial_val, **kwargs):
else:
output_writer = int_writer(output_signal, clk)
return clkgen, output_driver, drive_and_check, output_writer
@block
def canonical_list_writer(output_signal_list, clk):
@ -166,6 +171,7 @@ end process INITIAL_VALUE_BENCH_OUTPUT_WRITER;
'''
return list_writer
@block
def bool_list_writer(output_signal_list, clk):
@ -178,6 +184,7 @@ def bool_list_writer(output_signal_list, clk):
return list_writer
@block
def initial_value_bool_list_bench(initial_vals, **kwargs):
clk = Signal(bool(0))
@ -201,7 +208,7 @@ def initial_value_bool_list_bench(initial_vals, **kwargs):
def clkgen():
clk.next = 0
for n in range(N):
for dummy in range(N):
yield delay(10)
clk.next = not clk
@ -231,14 +238,17 @@ def initial_value_bool_list_bench(initial_vals, **kwargs):
return clkgen, output_driver, drive_and_check, output_writer
@block
def assign_output(input_signal, output_signal):
@always_comb
def assignment():
output_signal.next = input_signal
return assignment
@block
def initial_value_list_bench(initial_vals, **kwargs):
clk = Signal(bool(0))
@ -268,7 +278,7 @@ def initial_value_list_bench(initial_vals, **kwargs):
def clkgen():
clk.next = 0
for n in range(N):
for dummy in range(N):
yield delay(10)
clk.next = not clk
@ -315,14 +325,29 @@ def initial_value_mem_convert_bench():
inst = memory(clock, reset, wr, wrd, rdd, addr)
return inst
tCKhalf = 10 // 2
tReset = int (10 * 3.5)
@instance
def genclk():
while True:
clock.next = not clock
yield delay(tCKhalf)
@instance
def genreset():
reset.next = 0
yield delay(tReset)
reset.next = 1
return instances()
@block
def memory(clock, reset, wr, wrd, rdd, addr):
mem = [Signal(intbv(0, min=wrd.min, max=wrd.max))
for _ in range(addr.max)]
for __ in range(addr.max)]
inst_init = memory_init(mem)
@ -334,6 +359,7 @@ def memory(clock, reset, wr, wrd, rdd, addr):
return inst_init, beh_mem
@block
def memory_init(mem):
mem_size = len(mem)
@ -396,20 +422,23 @@ def test_signed():
runner(initial_val)
def test_bool():
'''The correct initial value should be used for bool type signal.
'''
initial_val = bool(randrange(0, 2))
runner(initial_val)
def test_modbv():
'''The correct initial value should be used for modbv type signal.
'''
initial_val = modbv(randrange(0, 2**10))[10:]
initial_val = modbv(randrange(0, 2 ** 10))[10:]
runner(initial_val)
def test_enum():
'''The correct initial value should be used for enum type signals.
'''
@ -420,16 +449,18 @@ def test_enum():
runner(val1, tb=initial_value_enum_bench, states=states)
runner(val2, tb=initial_value_enum_bench, states=states)
def test_long_signals():
'''The correct initial value should work with wide bitwidths (i.e. >32)
'''
min_val = -(2**71)
max_val = 2**71 - 1
min_val = -(2 ** 71)
max_val = 2 ** 71 - 1
initial_val = intbv(
randrange(min_val, max_val), min=min_val, max=max_val)
runner(initial_val)
def test_single_length_signals():
'''The correct initial value should be used for a single length signal
'''
@ -437,14 +468,14 @@ def test_single_length_signals():
runner(initial_val)
def test_unsigned_list():
'''The correct initial value should be used for unsigned type signal lists
'''
min_val = 0
max_val = 34
initial_vals = [intbv(
randrange(min_val, max_val), min=min_val, max=max_val)
for each in range(10)]
initial_vals = [intbv(randrange(min_val, max_val), min=min_val, max=max_val)
for __ in range(10)]
runner(initial_vals, tb=initial_value_list_bench)
@ -453,15 +484,15 @@ def test_unsigned_list():
intbv(randrange(min_val, max_val), min=min_val, max=max_val)] * 10
runner(initial_vals, tb=initial_value_list_bench)
def test_signed_list():
'''The correct initial value should be used for signed type signal lists
'''
min_val = -12
max_val = 4
initial_vals = [intbv(
randrange(min_val, max_val), min=min_val, max=max_val)
for each in range(10)]
initial_vals = [intbv(randrange(min_val, max_val), min=min_val, max=max_val)
for __ in range(10)]
runner(initial_vals, tb=initial_value_list_bench)
@ -471,17 +502,17 @@ def test_signed_list():
runner(initial_vals, tb=initial_value_list_bench)
def test_modbv_list():
'''The correct initial value should be used for modbv type signal lists
'''
initial_vals = [
modbv(randrange(0, 2**10))[10:] for each in range(10)]
initial_vals = [modbv(randrange(0, 2 ** 10))[10:] for __ in range(10)]
runner(initial_vals, tb=initial_value_list_bench)
# All the same case
initial_vals = [modbv(randrange(0, 2**10))[10:]] * 10
initial_vals = [modbv(randrange(0, 2 ** 10))[10:]] * 10
runner(initial_vals, tb=initial_value_list_bench)
@ -489,22 +520,22 @@ def test_long_signals_list():
'''The correct initial value should work with wide bitwidths (i.e. >32)
signal lists
'''
min_val = -(2**71)
max_val = 2**71 - 1
initial_vals = [intbv(
randrange(min_val, max_val), min=min_val, max=max_val)
for each in range(10)]
min_val = -(2 ** 71)
max_val = 2 ** 71 - 1
initial_vals = [intbv(randrange(min_val, max_val), min=min_val, max=max_val)
for __ in range(10)]
runner(initial_vals, tb=initial_value_list_bench)
# All the same case
initial_vals = [intbv(2**65-50, min=min_val, max=max_val)] * 10
initial_vals = [intbv(2 ** 65 - 50, min=min_val, max=max_val)] * 10
runner(initial_vals, tb=initial_value_list_bench)
def test_bool_signals_list():
'''The correct initial value should be used for a boolean type signal lists
'''
initial_vals = [False for each in range(10)]
initial_vals = [False for __ in range(10)]
runner(initial_vals, tb=initial_value_bool_list_bench)
@ -540,7 +571,8 @@ def test_memory_convert():
toVHDL.initial_values = True
try:
assert conversion.analyze(inst) == 0
# assert conversion.analyze(inst) == 0
assert inst.analyze_convert() == 0
finally:
toVerilog.initial_values = pre_xiv
@ -560,7 +592,7 @@ def init_reset_tb():
def clkgen():
clk.next = 0
for n in range(10):
for dummy in range(10):
yield delay(10)
clk.next = not clk
@ -573,7 +605,7 @@ def init_reset_tb():
yield clk.posedge
reset.next = 0
@always_seq(clk.posedge,reset=reset)
@always_seq(clk.posedge, reset=reset)
def seq():
print(s_large)
@ -591,10 +623,9 @@ def test_init_reset():
"""
inst = init_reset_tb()
assert conversion.verify(inst,initial_values=True) == 0
assert conversion.verify(inst, initial_values=True) == 0
#def test_init_used_list():
# def test_init_used_list():
# '''It should be the _init attribute of each element in the list
# that is used for initialisation
#
@ -612,4 +643,3 @@ def test_init_reset():
if __name__ == "__main__":
test_signed_list()

29
myhdl/test/conversion/general/test_intbv_signed.py
View File

@ -19,8 +19,8 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
""" Run the intbv.signed() unit tests. """
import myhdl
from myhdl import *
from myhdl import (block, intbv, delay, concat, instance, conversion)
@block
def PlainIntbv():
@ -131,13 +131,11 @@ def PlainIntbv():
b15 = a15.signed()
assert b15 == 0
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# in these cases the .signed() function should classify the
# value of the intbv instance as signed and return the value as is
#
# set bit #3 and increase the range that the set bit is actually the
# msb, but due to the negative range not considered signed
# Expect to return 4
@ -156,7 +154,7 @@ def PlainIntbv():
a23 = intbv(4, min=-1, max=8)
b23 = a23.signed()
assert b23 == 4
# intbv with negative range, pos number, and msb set, return signed()
# Expect the number to returned as is
a24 = intbv(7, min=-1, max=8)
@ -195,7 +193,6 @@ def PlainIntbv():
return logic
@block
def SlicedSigned():
'''Test a slice with .signed()
@ -204,6 +201,7 @@ def SlicedSigned():
min=0 and max > min, which will result in an intbv instance that
will be considered unsigned by the intbv.signed() function.
'''
@instance
def logic():
b = intbv(4, min=-8, max=8)
@ -213,12 +211,12 @@ def SlicedSigned():
b[:] = a[4:]
assert b == 4
b[:] = a[4:].signed()
assert b == 4 # msb is not set with a 4 bit slice
assert b == 4 # msb is not set with a 4 bit slice
b[:] = a[3:]
assert b == 4
b[:] = a[3:].signed()
assert b == -4 # msb is set with 3 bits sliced
assert b == -4 # msb is set with 3 bits sliced
return logic
@ -231,7 +229,7 @@ def SignedConcat():
def logic():
print("Signed Concat test")
yield delay(10)
# concat 3 bits
# Expect the signed function to return a negative value
a = intbv(0)[3:]
@ -242,17 +240,20 @@ def SignedConcat():
# concat a 3 bit intbv with msb set and two bits
# Expect a negative number
b = intbv(5,min=0,max=8)
b = intbv(5, min=0, max=8)
assert concat(b, True, True).signed() == -9
return logic
def test_PlainIntbv():
assert conversion.verify(PlainIntbv()) == 0
def test_SlicedSigned():
assert conversion.verify(SlicedSigned()) == 0
def test_SignedConcat():
assert conversion.verify(SignedConcat()) == 0

3
myhdl/test/conversion/general/test_interfaces1.py
View File

@ -1,8 +1,9 @@
from myhdl import (block, Signal, ResetSignal, intbv, always_seq,
instance, delay, StopSimulation, )
instance, delay, StopSimulation,)
class MyIntf(object):
def __init__(self):
self.x = Signal(intbv(2, min=0, max=16))
self.y = Signal(intbv(3, min=0, max=18))

36
myhdl/test/conversion/general/test_interfaces3.py
View File

@ -1,37 +1,41 @@
import sys
import myhdl
from myhdl import (block, Signal, ResetSignal, intbv, always_comb, always_seq,
instance, delay, StopSimulation, )
instance, delay, StopSimulation, instances)
class Intf1:
def __init__(self, x):
self.x = Signal(intbv(0, min=x.min, max=x.max))
class Intf2:
def __init__(self, y):
self.y = Signal(intbv(0, min=y.min, max=y.max))
class ZBus:
def __init__(self, z):
self.z = Signal(intbv(0, min=z.min, max=z.max))
class Intf3:
def __init__(self, z):
self.z = ZBus(z)
class IntfWithConstant1:
def __init__(self):
self.const1 = 707
self.const2 = 3
class IntfWithConstant2:
def __init__(self):
self.a = 9
self.b = 10
@ -41,17 +45,21 @@ class IntfWithConstant2:
@block
def assign(y, x):
@always_comb
def beh_assign():
y.next = x
return beh_assign
@block
def assign_intf(x, y):
@always_comb
def rtl():
x.x.next = y.y
return rtl
@ -67,7 +75,7 @@ def top_assign(x, y, z):
inst2 = assign(i2.y, y) # i2.y = y
inst3 = assign_intf(i1, i2)
return myhdl.instances()
return instances()
@block
@ -83,15 +91,17 @@ def c_testbench_one():
yield delay(10)
print("x: %d" % (x,))
assert x == 3
return tb_dut, tb_stim
@block
def multi_comb(x, y, z):
@always_comb
def rtl():
x.x.next = y.y + z.z.z
return rtl
@ -102,7 +112,7 @@ def top_multi_comb(x, y, z):
it only tests intermediate interfaces.
"""
intf = Intf1(x), Intf2(y), Intf3(z)
x.assign(intf[0].x)
x.assign(intf[0].x)
intf[1].y.assign(y)
intf[2].z.z.assign(z)
inst = multi_comb(*intf)
@ -122,22 +132,22 @@ def c_testbench_two():
yield delay(10)
print("x: %d" % (x,))
assert x == 5
return tb_dut, tb_stim
@block
def top_const(clock, reset, x, y, intf):
@always_seq(clock.posedge, reset=reset)
def rtl1():
v = intf.a**3 + intf.b**3
v = intf.a ** 3 + intf.b ** 3
x.next = v - intf.c
@always_comb
def rtl2():
y.next = x + intf.more_constants.const1 - \
intf.more_constants.const2*235 - 2
intf.more_constants.const2 * 235 - 2
return rtl1, rtl2
@ -155,14 +165,14 @@ def c_testbench_three():
intf = IntfWithConstant2()
tbdut = top_const(clock, reset, x, y, intf)
@instance
def tbclk():
clock.next = False
while True:
yield delay(3)
clock.next = not clock
@instance
def tbstim():
reset.next = reset.active
@ -182,7 +192,7 @@ def c_testbench_three():
def test_one_analyze():
x, y, z = [Signal(intbv(0, min=-8, max=8))
for _ in range(3)]
# fool name check in convertor
# fool name check in convertor
# to be reviewed
x._name = 'x'
y._name = 'y'

18
myhdl/test/conversion/general/test_interfaces4.py
View File

@ -1,7 +1,5 @@
import sys
import myhdl
from myhdl import (block, Signal, ResetSignal, modbv, always_seq, concat,
instance, delay, StopSimulation)
from myhdl.conversion import analyze, verify
@ -15,6 +13,7 @@ to be a name collision in the name expansion and was introduced in
class Intf1(object):
def __init__(self):
self.sig1 = Signal(bool(0))
self.sig2 = Signal(bool(0))
@ -22,6 +21,7 @@ class Intf1(object):
class Intf2(object):
def __init__(self):
self.sig1 = Signal(bool(0))
self.sig2 = Signal(bool(0))
@ -31,7 +31,7 @@ class Intf2(object):
@block
def use_nested_intf(clock, reset, intf1, intf2):
sig1 = Signal(bool(0))
sig2 = Signal(bool(0))
@ -61,19 +61,19 @@ def something_peculiar(clock, reset, intf1, intf2):
# remove the if/else and leave just the line in the
# if clause the error does not occur, inlcude the if/else
# and the error occurs
if intf1.sig3 > 0: # remove no error
if intf1.sig3 > 0: # remove no error
intf2.sig1.next = not intf1.sig1
intf2.sig2.next = not intf1.sig2
intf2.sig3.next = intf1.sig3 + intf2.sig3
else: # remove no error
intf2.sig3.next = 0 # remove no error
else: # remove no error
intf2.sig3.next = 0 # remove no error
return proc
@block
def interfaces_top(clock, reset, sdi, sdo, nested):
intf1, intf2, intf3 = Intf1(), Intf2(), Intf1()
inst1 = use_nested_intf(clock, reset, intf1, intf2)
@ -104,13 +104,13 @@ def c_testbench_one():
nested = Signal(bool())
tbdut = interfaces_top(clock, reset, sdi, sdo, nested)
@instance
@instance
def tbclk():
clock.next = False
while True:
yield delay(3)
clock.next = not clock
# there is an issue when using bools with variables and
# VHDL conversion, this might be an expected limitation?
# expected = (False, False, False, True, True, True,

90
myhdl/test/conversion/general/test_listofsigs.py
View File

@ -1,14 +1,15 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always_comb,
always, instance, StopSimulation,
conversion)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
N = 8
M= 2**N
M = 2 ** N
### A first case that already worked with 5.0 list of signal constraints ###
@block
def intbv2list():
"""Conversion between intbv and list of boolean signals."""
@ -40,52 +41,63 @@ def intbv2list():
# test
def test_intbv2list():
assert conversion.verify(intbv2list()) == 0
### A number of cases with relaxed constraints, for various decorator types ###
@block
def inv1(z, a):
@always(a)
def logic():
z.next = not a
return logic
@block
def inv2(z, a):
@always_comb
def logic():
z.next = not a
return logic
@block
def inv3(z, a):
@instance
def logic():
while True:
yield a
z.next = not a
return logic
@block
def inv4(z, a):
@instance
def logic():
while True:
yield a
yield delay(1)
z.next = not a
return logic
@block
def case1(z, a, inv):
b = [Signal(bool(1)) for i in range(len(a))]
c = [Signal(bool(0)) for i in range(len(a))]
b = [Signal(bool(1)) for __ in range(len(a))]
c = [Signal(bool(0)) for __ in range(len(a))]
@always(a)
def extract():
for i in range(len(a)):
@ -105,8 +117,9 @@ def case1(z, a, inv):
@block
def case2(z, a, inv):
b = [Signal(bool(1)) for i in range(len(a))]
c = [Signal(bool(0)) for i in range(len(a))]
b = [Signal(bool(1)) for __ in range(len(a))]
c = [Signal(bool(0)) for __ in range(len(a))]
@always_comb
def extract():
for i in range(len(a)):
@ -126,8 +139,9 @@ def case2(z, a, inv):
@block
def case3(z, a, inv):
b = [Signal(bool(1)) for i in range(len(a))]
c = [Signal(bool(0)) for i in range(len(a))]
b = [Signal(bool(1)) for __ in range(len(a))]
c = [Signal(bool(0)) for __ in range(len(a))]
@instance
def extract():
while True:
@ -151,8 +165,9 @@ def case3(z, a, inv):
@block
def case4(z, a, inv):
b = [Signal(bool(1)) for i in range(len(a))]
c = [Signal(bool(0)) for i in range(len(a))]
b = [Signal(bool(1)) for __ in range(len(a))]
c = [Signal(bool(0)) for __ in range(len(a))]
@instance
def extract():
while True:
@ -176,10 +191,6 @@ def case4(z, a, inv):
return extract, inst, assemble
@block
def processlist(case, inv):
"""Extract list from intbv, do some processing, reassemble."""
@ -201,31 +212,34 @@ def processlist(case, inv):
return case_inst, stimulus
# functional tests
def test_processlist11():
assert conversion.verify(processlist(case1, inv1)) == 0
def test_processlist12():
assert conversion.verify(processlist(case1, inv2))== 0
assert conversion.verify(processlist(case1, inv2)) == 0
def test_processlist22():
assert conversion.verify(processlist(case2, inv2))== 0
assert conversion.verify(processlist(case2, inv2)) == 0
def test_processlist33():
assert conversion.verify(processlist(case3, inv3))== 0
assert conversion.verify(processlist(case3, inv3)) == 0
def test_processlist44():
assert conversion.verify(processlist(case4, inv4))== 0
assert conversion.verify(processlist(case4, inv4)) == 0
# signed and unsigned
@block
def unsigned():
z = Signal(intbv(0)[8:])
a = [Signal(intbv(0)[8:]) for i in range(3)]
a = [Signal(intbv(0)[8:]) for __ in range(3)]
@always_comb
def logic():
@ -248,7 +262,7 @@ def test_unsigned():
@block
def signed():
z = Signal(intbv(0, min=-10, max=34))
a = [Signal(intbv(0, min=-5, max=17)) for i in range(3)]
a = [Signal(intbv(0, min=-5, max=17)) for __ in range(3)]
@always_comb
def logic():
@ -271,8 +285,8 @@ def test_signed():
@block
def mixed():
z = Signal(intbv(0, min=0, max=34))
a = [Signal(intbv(0, min=-11, max=17)) for i in range(3)]
b = [Signal(intbv(0)[5:]) for i in range(3)]
a = [Signal(intbv(0, min=-11, max=17)) for __ in range(3)]
b = [Signal(intbv(0)[5:]) for __ in range(3)]
@always_comb
def logic():
@ -291,11 +305,11 @@ def mixed():
def test_mixed():
conversion.verify(mixed())
### error tests
# ## error tests
# port in list
@block
def portInList(z, a, b):
@ -309,7 +323,7 @@ def portInList(z, a, b):
def test_portInList():
z, a, b = [Signal(intbv(0)[8:]) for i in range(3)]
z, a, b = [Signal(intbv(0)[8:]) for __ in range(3)]
try:
inst = conversion.analyze(portInList(z, a, b))
@ -318,13 +332,13 @@ def test_portInList():
else:
assert False
# signal in multiple lists
@block
def sigInMultipleLists():
z, a, b = [Signal(intbv(0)[8:]) for i in range(3)]
z, a, b = [Signal(intbv(0)[8:]) for __ in range(3)]
m1 = [a, b]
m2 = [a, b]
@ -335,6 +349,7 @@ def sigInMultipleLists():
return logic
def test_sigInMultipleLists():
try:
@ -346,19 +361,23 @@ def test_sigInMultipleLists():
# list of signals as port
@block
def my_register(clk, inp, outp):
@always(clk.posedge)
def my_register_impl():
for index in range(len(inp)):
outp[index].next = inp[index]
return my_register_impl
def test_listAsPort():
count = 3
clk = Signal(False)
inp = [Signal(intbv(0)[8:0]) for index in range(count)]
outp = [Signal(intbv(0)[8:0]) for index in range(count)]
inp = [Signal(intbv(0)[8:0]) for __ in range(count)]
outp = [Signal(intbv(0)[8:0]) for __ in range(count)]
try:
inst = conversion.analyze(my_register(clk, inp, outp))
except ConversionError as e:
@ -366,6 +385,3 @@ def test_listAsPort():
else:
assert False

16
myhdl/test/conversion/general/test_loops.py
View File

@ -2,8 +2,7 @@ import os
path = os.path
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance, downrange)
from myhdl.conversion import verify, analyze
from myhdl import ConversionError
from myhdl.conversion._misc import _error
@ -215,7 +214,6 @@ def NestedForLoop2(a, out):
def logic():
while 1:
yield a
var = 0
out.next = 0
for i in downrange(len(a)):
if a[i] == 0:
@ -321,7 +319,6 @@ def WhileBreakLoop(a, out):
def logic():
while 1:
yield a
var = 0
i = len(a) - 1
out.next = 0
while i >= 0:
@ -340,7 +337,6 @@ def WhileBreakContinueLoop(a, out):
def logic():
while 1:
yield a
var = 0
i = len(a) - 1
out.next = 0
while i >= 0:
@ -409,23 +405,23 @@ def testForLoop5():
def testForContinueLoop():
assert verify(LoopBench(ForContinueLoop)) == 0
assert verify(LoopBench(ForContinueLoop)) == 0
def testForBreakLoop():
assert verify(LoopBench(ForBreakLoop)) == 0
assert verify(LoopBench(ForBreakLoop)) == 0
def testForBreakContinueLoop():
assert verify(LoopBench(ForBreakContinueLoop)) == 0
assert verify(LoopBench(ForBreakContinueLoop)) == 0
def testNestedForLoop1():
assert verify(LoopBench(NestedForLoop1)) == 0
assert verify(LoopBench(NestedForLoop1)) == 0
def testNestedForLoop2():
assert verify(LoopBench(NestedForLoop2)) == 0
assert verify(LoopBench(NestedForLoop2)) == 0
def testFunctionCall():

242
myhdl/test/conversion/general/test_match_py310.py
View File

@ -1,19 +1,21 @@
import sys
from myhdl import *
import pytest
from myhdl import (block, Signal, enum, intbv, delay, always_comb,
always, instance, instances, StopSimulation,
concat
)
# SELOPTS = enum('SEL0', 'SEL1', 'SEL2', 'SEL3')
#SELOPTS = enum('SEL0', 'SEL1', 'SEL2', 'SEL3')
@block
def mux4a(
sel,
in0,
in1,
in2,
in3,
sel,
in0,
in1,
in2,
in3,
out0
):
@always_comb
def rtl():
if sel == 0:
@ -27,8 +29,10 @@ def mux4a(
return instances()
@block
def mux4b(sel, in0, in1, in2, in3, out0):
@always_comb
def rtl():
match sel:
@ -40,10 +44,13 @@ def mux4b(sel, in0, in1, in2, in3, out0):
out0.next = in2
case _:
out0.next = in3
return instances()
@block
def mux4c(sel, in0, in1, in3, out0):
@always_comb
def rtl():
match sel:
@ -53,22 +60,25 @@ def mux4c(sel, in0, in1, in3, out0):
out0.next = in1
case _:
out0.next = in3
return instances()
t_opts = enum('SEL0', 'SEL1', 'SEL2', 'SEL3')
@block
def enumMux4a(
sel,
in0,
in1,
in2,
in3,
sel,
in0,
in1,
in2,
in3,
out0,
):
sel_enum = Signal(t_opts.SEL0)
@always_comb
def mapping():
if 0 == sel:
@ -79,8 +89,7 @@ def enumMux4a(
sel_enum.next = t_opts.SEL2
elif 3 == sel:
sel_enum.next = t_opts.SEL3
@always_comb
def rtl():
if sel_enum == t_opts.SEL0:
@ -94,17 +103,11 @@ def enumMux4a(
return instances()
@block
def enumMux4b(
sel,
in0,
in1,
in2,
in3,
out0,
):
def enumMux4b(sel, in0, in1, in2, in3, out0):
sel_enum = Signal(t_opts.SEL0)
@always_comb
def mapping():
if 0 == sel:
@ -115,8 +118,7 @@ def enumMux4b(
sel_enum.next = t_opts.SEL2
elif 3 == sel:
sel_enum.next = t_opts.SEL3
@always_comb
def rtl():
match sel_enum:
@ -127,58 +129,61 @@ def enumMux4b(
case t_opts.SEL2:
out0.next = in2
case _:
out0.next = in3
out0.next = in3
return instances()
t_fsma_opts = enum('IDLE', 'READ', 'WRITE', 'ERROR')
@block
def fsm4a(
clk,
rst,
rd,
wr,
clk,
rst,
rd,
wr,
):
smp = Signal(t_fsma_opts.IDLE)
@always(clk.posedge)
def rtl():
if rst:
smp.next = t_fsma_opts.IDLE
smp.next = t_fsma_opts.IDLE
else:
match smp:
case t_fsma_opts.IDLE:
smp.next = t_fsma_opts.IDLE
smp.next = t_fsma_opts.IDLE
if rd:
smp.next = t_fsma_opts.READ
smp.next = t_fsma_opts.READ
if wr:
smp.next = t_fsma_opts.WRITE
smp.next = t_fsma_opts.WRITE
case t_fsma_opts.READ:
smp.next = t_fsma_opts.IDLE
smp.next = t_fsma_opts.IDLE
case t_fsma_opts.WRITE:
smp.next = t_fsma_opts.IDLE
smp.next = t_fsma_opts.IDLE
case _:
smp.next = t_fsma_opts.IDLE
smp.next = t_fsma_opts.IDLE
return instances()
@block
def fsm4b(
clk,
a,
b,
c,
z,
clk,
a,
b,
c,
z,
):
@always(clk.posedge)
def rtl():
match concat(a,b,c):
case intbv(0b111) :
match concat(a, b, c):
case intbv(0b111):
z.next = 0x6
case intbv(0b101) | intbv(0b110) :
case intbv(0b101) | intbv(0b110):
z.next = 0x7
case _:
z.next = 0x0
@ -186,22 +191,21 @@ def fsm4b(
return instances()
@block
def muxBench0(setup=0):
clk = Signal(bool(0))
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
clk = Signal(bool(0))
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
@instance
def clkgen():
clk.next = 1
for i in range(400):
for dummy in range(400):
yield delay(10)
clk.next = not clk
@ -239,7 +243,7 @@ def muxBench0(setup=0):
yield clk.posedge
assert out0 == 0xa
yield clk.posedge
if 0 == setup:
i_mux = mux4a(sel, in0, in1, in2, in3, out0)
elif 1 == setup:
@ -249,117 +253,123 @@ def muxBench0(setup=0):
else:
i_mux = enumMux4b(sel, in0, in1, in2, in3, out0)
return instances()
return i_mux
def test_mux4a_convert():
clk = Signal(bool(0))
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
i_dut = mux4a(sel, in0, in1, in2, in3, out0)
assert i_dut.analyze_convert() == 0
def test_muxBench0():
sim = muxBench0(0)
sim.run_sim()
def test_muxBench0_convert():
i_dut = muxBench0(0)
assert i_dut.analyze_convert() == 0
#@pytest.mark.skipif(sys.version_info < (3, 10), reason="requires python3.10 or higher")
# @pytest.mark.skipif(sys.version_info < (3, 10), reason="requires python3.10 or higher")
def test_mux4b_convert():
clk = Signal(bool(0))
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
i_dut = mux4b(sel, in0, in1, in2, in3, out0)
assert i_dut.analyze_convert() == 0
#@pytest.mark.skipif(sys.version_info < (3, 10), reason="requires python3.10 or higher")
def test_mux4b_convert():
clk = Signal(bool(0))
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
# @pytest.mark.skipif(sys.version_info < (3, 10), reason="requires python3.10 or higher")
def test_mux4c_convert():
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
i_dut = mux4c(sel, in0, in1, in3, out0)
assert i_dut.analyze_convert() == 0
#@pytest.mark.skipif(sys.version_info < (3, 10), reason="requires python3.10 or higher")
# @pytest.mark.skipif(sys.version_info < (3, 10), reason="requires python3.10 or higher")
def test_muxBench1():
sim = muxBench0(1)
sim.run_sim()
#@pytest.mark.skipif(sys.version_info < (3, 10), reason="requires python3.10 or higher")
# @pytest.mark.skipif(sys.version_info < (3, 10), reason="requires python3.10 or higher")
def test_muxBench1_convert():
i_dut = muxBench0(1)
assert i_dut.analyze_convert() == 0
def test_muxBench2():
sim = muxBench0(2)
sim.run_sim()
def test_muxBench2_convert():
i_dut = muxBench0(2)
assert i_dut.analyze_convert() == 0
def test_enumMux4a_convert():
clk = Signal(bool(0))
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
i_dut = enumMux4a(sel, in0, in1, in2, in3, out0)
assert i_dut.analyze_convert() == 0
def test_muxBench3():
sim = muxBench0(3)
sim.run_sim()
def test_enumMux4b_convert():
clk = Signal(bool(0))
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
sel = Signal(intbv(0)[2:])
in0 = Signal(intbv(0)[4:])
in1 = Signal(intbv(0)[4:])
in2 = Signal(intbv(0)[4:])
in3 = Signal(intbv(0)[4:])
out0 = Signal(intbv(0)[4:])
i_dut = enumMux4b(sel, in0, in1, in2, in3, out0)
assert i_dut.analyze_convert() == 0
def test_fsm4a_convert():
clk = Signal(bool(0))
rst = Signal(intbv(0)[1:])
rd = Signal(intbv(0)[1:])
wr = Signal(intbv(0)[1:])
clk = Signal(bool(0))
rst = Signal(intbv(0)[1:])
rd = Signal(intbv(0)[1:])
wr = Signal(intbv(0)[1:])
i_dut = fsm4a(clk, rst, rd, wr)
assert i_dut.analyze_convert() == 0
def test_fsm4b_convert():
clk = Signal(bool(0))
a = Signal(intbv(0)[1:])
b = Signal(intbv(0)[1:])
c = Signal(intbv(0)[1:])
z = Signal(intbv(0)[3:])
def test_fsm4b_convert():
clk = Signal(bool(0))
a = Signal(intbv(0)[1:])
b = Signal(intbv(0)[1:])
c = Signal(intbv(0)[1:])
z = Signal(intbv(0)[3:])
i_dut = fsm4b(clk, a, b, c, z)
assert i_dut.analyze_convert() == 0

61
myhdl/test/conversion/general/test_method.py
View File

@ -1,9 +1,11 @@
import sys
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always_comb,
always, instance, StopSimulation)
from myhdl._Simulation import Simulation
from myhdl.conversion import verify
class HdlObj(object):
def __init__(self):
pass
@ -11,6 +13,7 @@ class HdlObj(object):
def method_func(self, clk, srst, x, y):
z = Signal(intbv(0, min=y.min, max=y.max))
ifx = self._mfunc(x, z)
@always(clk.posedge)
def hdl():
if srst:
@ -22,22 +25,29 @@ class HdlObj(object):
@block
def _mfunc(self, x, y):
@always_comb
def _hdl():
y.next = x + 1
return _hdl
@block
def _func(x,y):
def _func(x, y):
@always_comb
def _hdl():
y.next = x + 1
return _hdl
class HdlObjObj(object):
def __init__(self):
pass
@block
def method_func(self, clk, srst, x, y):
z1 = Signal(intbv(0, min=y.min, max=y.max))
@ -45,7 +55,7 @@ class HdlObjObj(object):
hobj = HdlObj()
ifx1 = hobj._mfunc(x, z1)
ifx2 = _func(x, z2)
@always(clk.posedge)
def hdl():
if srst:
@ -53,28 +63,33 @@ class HdlObjObj(object):
else:
y.next = x + z1 + (z1 - z2)
return hdl, ifx1, ifx2
return hdl, ifx1, ifx2
class HdlObjAttrSimple(object):
def __init__(self):
self.AConstant = 3
@block
def method_func(self, clk, srst, x, y):
# limitation for class method conversion, the object attributes
# can only be used/accessed during elaboration.
AConstant = int(self.AConstant)
@always(clk.posedge)
def hdl():
if srst:
y.next = 0
else:
y.next = x + (x+1) + AConstant - 3
y.next = x + (x + 1) + AConstant - 3
return hdl
class HdlObjAttr(object):
def __init__(self, clk, srst, x, y):
self.clk = clk
self.srst = srst
@ -82,10 +97,11 @@ class HdlObjAttr(object):
self.y = y
self.z = Signal(intbv(0, min=y.min, max=y.max))
self.hobj = HdlObj()
@block
def method_func(self):
ifx = self.hobj._mfunc(self.x, self.z)
@always(self.clk.posedge)
def hdl():
if self.srst:
@ -95,6 +111,7 @@ class HdlObjAttr(object):
return hdl, ifx
@block
def ObjBench(hObj):
@ -113,8 +130,7 @@ def ObjBench(hObj):
hdlobj_inst = hObj()
hdl_inst = hdlobj_inst.method_func(clk, srst, x, y)
else:
raise StandardError("Incorrect hOjb %s" % (type(hObj), str(hObj)))
raise ValueError("Incorrect hOjb %s" % (type(hObj), str(hObj)))
@instance
def tb_clkgen():
@ -125,12 +141,12 @@ def ObjBench(hObj):
yield delay(10)
srst.next = False
yield delay(10)
for i in range(1000):
for dummy in range(1000):
yield delay(10)
clk.next = not clk
xtable = (1,2,3,4,5,6)
ytable = (3,5,7,9,11,13)
xtable = (1, 2, 3, 4, 5, 6)
ytable = (3, 5, 7, 9, 11, 13)
@instance
def tb_stimulus():
@ -153,20 +169,23 @@ def ObjBench(hObj):
def test_hdlobj():
assert verify(ObjBench(HdlObj)) == 0
def test_hdlobjobj():
assert verify(ObjBench(HdlObjObj)) == 0
def test_hdlobjattrsimple():
assert verify(ObjBench(HdlObjAttrSimple)) == 0
#def test_hdlobjattr():
# # object attributes currently not supported, these
# # tests are for class method conversion only and not
# def test_hdlobjattr():
# # object attributes currently not supported, these
# # tests are for class method conversion only and not
# # class attribute conversion. When (if) class attribute
# # is supported remove this test.
# # is supported remove this test.
# assert verify(ObjBench, HdlObjAttr) == 1
if __name__ == '__main__':
Simulation(ObjBench(HdlObj)).run()
Simulation(ObjBench(HdlObjAttrSimple)).run()

18
myhdl/test/conversion/general/test_nonlocal.py
View File

@ -1,14 +1,15 @@
import os
path = os.path
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always_seq,
ResetSignal, instance, StopSimulation
)
@block
def NonlocalBench():
ALL_ONES = 2**7-1
ALL_ONES = 2 ** 7 - 1
ONE = 1
qout = Signal(intbv(ONE)[8:])
@ -21,10 +22,10 @@ def NonlocalBench():
@always_seq(clk.posedge, reset=reset)
def scrambler():
if init:
q[8:1] = ALL_ONES
q[8:1] = ALL_ONES
else:
q[0] = q[7] ^ q[6]
q[8:1] = q[7:0]
q[8:1] = q[7:0]
qout.next = q[8:1]
@instance
@ -44,7 +45,7 @@ def NonlocalBench():
print(qout)
assert qout == ONE
reset.next = 0
for i in range(100):
for dummy in range(100):
yield clk.negedge
print(qout)
init.next = 1
@ -52,12 +53,11 @@ def NonlocalBench():
assert qout == ALL_ONES
print(qout)
init.next = 0
for i in range(300):
for dummy in range(300):
print(qout)
raise StopSimulation()
return scrambler, clkgen, stimulus
return scrambler, clkgen, stimulus
def test_nonlocal():

13
myhdl/test/conversion/general/test_numass.py
View File

@ -1,7 +1,6 @@
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance, conversion)
@block
@ -10,9 +9,9 @@ def NumassBench():
p = Signal(intbv(1)[8:])
q = Signal(intbv(1)[40:])
r = Signal(intbv(1, min=-256, max=256))
s = Signal(intbv(1, min=-2**40, max=2**40))
PBIGINT = randrange(2**34, 2**40)
NBIGINT = -randrange(2**34, 2**40)
s = Signal(intbv(1, min=-2 ** 40, max=2 ** 40))
PBIGINT = randrange(2 ** 34, 2 ** 40)
NBIGINT = -randrange(2 ** 34, 2 ** 40)
@instance
def check():
@ -39,13 +38,13 @@ def NumassBench():
r.next = 255
s.next = -246836311517
yield delay(10)
print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0]))
print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r , s[41:20], s[20:0]))
p.next = 254
q.next = PBIGINT
r.next = -256
s.next = NBIGINT
yield delay(10)
print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r ,s[41:20], s[20:0]))
print("%d %d %d %d %d %d" % (p, q[40:20], q[20:0], r , s[41:20], s[20:0]))
return check

98
myhdl/test/conversion/general/test_print.py
View File

@ -1,10 +1,10 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, enum, intbv, delay, instance)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
t_State = enum("START", "RUN", "STOP")
@block
def PrintBench():
si1 = Signal(intbv(0)[8:])
@ -44,7 +44,7 @@ def PrintBench():
print("i1 %s i2 %s b %s si1 %s si2 %s" % (i1, i2, b, si1, si2))
print("i1 %d i2 %d b %d si1 %d si2 %d" % (i1, i2, b, si1, si2))
print(b)
#print "%% %s" % i1
# print "%% %s" % i1
yield delay(10)
print(state)
@ -66,19 +66,20 @@ def PrintBench():
return logic
def testPrint():
assert PrintBench().verify_convert() == 0
@block
def PrintLongVectorsBench():
N84 = 84
M84 = 2**N84-1
M84 = 2 ** N84 - 1
N85 = 85
M85 = 2**N85-1
M85 = 2 ** N85 - 1
N86 = 86
M86 = 2**N86-1
M86 = 2 ** N86 - 1
N87 = 87
M87 = 2**N87-1
si1 = Signal(intbv(0)[N87:])
si2 = Signal(intbv(0, min=-M85, max=M86))
@ -106,19 +107,24 @@ def PrintLongVectorsBench():
return logic
def testPrintLongVectors():
assert PrintLongVectorsBench().verify_convert() == 0
# format string errors and unsupported features
@block
def PrintError1():
@instance
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print("floating point %f end" % i1)
return logic
@instance
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print("floating point %f end" % i1)
return logic
def testPrintError1():
try:
@ -128,14 +134,18 @@ def testPrintError1():
else:
assert False
@block
def PrintError2():
@instance
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print("begin %s %s end" % i1)
return logic
@instance
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print("begin %s %s end" % i1)
return logic
def testPrintError2():
try:
@ -145,15 +155,19 @@ def testPrintError2():
else:
assert False
@block
def PrintError3():
@instance
def logic():
i1 = intbv(12)[8:]
i2 = intbv(13)[8:]
yield delay(10)
print("begin %s end" % (i1, i2))
return logic
@instance
def logic():
i1 = intbv(12)[8:]
i2 = intbv(13)[8:]
yield delay(10)
print("begin %s end" % (i1, i2))
return logic
def testPrintError3():
try:
@ -163,14 +177,18 @@ def testPrintError3():
else:
assert False
@block
def PrintError4():
@instance
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print("%10s" % i1)
return logic
@instance
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print("%10s" % i1)
return logic
def testPrintError4():
try:
@ -180,14 +198,18 @@ def testPrintError4():
else:
assert False
@block
def PrintError5():
@instance
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print("%-10s" % i1)
return logic
@instance
def logic():
i1 = intbv(12)[8:]
yield delay(10)
print("%-10s" % i1)
return logic
def testPrintError5():
try:

54
myhdl/test/conversion/general/test_ram.py
View File

@ -1,9 +1,11 @@
import os
path = os.path
import unittest
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always_comb,
always, instance, StopSimulation,
conversion
)
@block
def ram1(dout, din, addr, we, clk, depth=128):
@ -11,22 +13,22 @@ def ram1(dout, din, addr, we, clk, depth=128):
@instance
def logic():
mem = [intbv(0)[8:] for i in range(depth)]
a = intbv(0)[8:]
mem = [intbv(0)[8:] for dummy in range(depth)]
while 1:
yield clk.posedge
if we:
ad = int(addr)
mem[int(addr)][:] = din
dout.next = mem[int(addr)]
return logic
@block
def ram_clocked(dout, din, addr, we, clk, depth=128):
""" Ram model """
mem = [Signal(intbv(0)[8:]) for i in range(depth)]
mem = [Signal(intbv(0)[8:]) for __ in range(depth)]
@instance
def access():
while 1:
@ -34,14 +36,15 @@ def ram_clocked(dout, din, addr, we, clk, depth=128):
if we:
mem[int(addr)].next = din
dout.next = mem[int(addr)]
return access
@block
def ram_deco1(dout, din, addr, we, clk, depth=128):
""" Ram model """
mem = [Signal(intbv(0)[8:]) for i in range(depth)]
mem = [Signal(intbv(0)[8:]) for __ in range(depth)]
@instance
def write():
@ -49,25 +52,25 @@ def ram_deco1(dout, din, addr, we, clk, depth=128):
yield clk.posedge
if we:
mem[int(addr)].next = din
@always_comb
def read():
dout.next = mem[int(addr)]
return write, read
@block
def ram_deco2(dout, din, addr, we, clk, depth=128):
""" Ram model """
mem = [Signal(intbv(0)[8:]) for i in range(depth)]
mem = [Signal(intbv(0)[8:]) for __ in range(depth)]
@always(clk.posedge)
def write():
if we:
mem[int(addr)].next = din
@always_comb
def read():
dout.next = mem[int(addr)]
@ -77,18 +80,18 @@ def ram_deco2(dout, din, addr, we, clk, depth=128):
@block
def ram2(dout, din, addr, we, clk, depth=128):
memL = [Signal(intbv()[len(dout):]) for i in range(depth)]
memL = [Signal(intbv()[len(dout):]) for __ in range(depth)]
@instance
def wrLogic() :
def wrLogic():
while 1:
yield clk.posedge
if we:
memL[int(addr)].next = din
@instance
def rdLogic() :
def rdLogic():
while 1:
yield clk.posedge
dout.next = memL[int(addr)]
@ -100,7 +103,6 @@ def ram2(dout, din, addr, we, clk, depth=128):
def RamBench(ram, depth=128):
dout = Signal(intbv(0)[8:])
dout_v = Signal(intbv(0)[8:])
din = Signal(intbv(0)[8:])
addr = Signal(intbv(0)[7:])
we = Signal(bool(0))
@ -138,14 +140,18 @@ def RamBench(ram, depth=128):
def testram_deco1():
assert conversion.verify(RamBench(ram_deco1)) == 0
def testram_deco2():
assert conversion.verify(RamBench(ram_deco2)) == 0
def testram_clocked():
assert conversion.verify(RamBench(ram_clocked)) == 0
def test2():
assert conversion.verify(RamBench(ram2)) == 0
def test1():
assert conversion.verify(RamBench(ram1)) == 0

44
myhdl/test/conversion/general/test_randscrambler.py
View File

@ -1,35 +1,35 @@
import os
path = os.path
import unittest
from unittest import TestCase
import random
from random import randrange
random.seed(2)
import time
import myhdl
from myhdl import *
from myhdl.conversion import verify
from random import seed, shuffle
seed('We want repeatable randomness')
from myhdl import (block, Signal, modbv, intbv, delay, instance, conversion)
N = 8
M = 2 ** N
DEPTH = 5
@block
def xor(z, a, b, c):
@instance
def logic():
while 1:
yield a, b, c
z.next = a ^ b ^ c
return logic
def randOthers(i, n):
l = list(range(n))
l.remove(i)
random.shuffle(l)
shuffle(l)
return l[0], l[1]
@block
def randscrambler(ol, il, stage=0):
""" Recursive hierarchy of random xor gates.
@ -38,8 +38,8 @@ def randscrambler(ol, il, stage=0):
"""
sl1 = [Signal(bool()) for i in range(N)]
sl2 = [Signal(bool()) for i in range(N)]
sl1 = [Signal(bool()) for __ in range(N)]
sl2 = [Signal(bool()) for __ in range(N)]
i1 = [None] * N
i2 = [None] * N
@ -47,7 +47,7 @@ def randscrambler(ol, il, stage=0):
for i in range(N):
j, k = randOthers(i, N)
i1[i] = xor(sl1[i], il[i], il[j], il[k])
rs = randscrambler(sl2, sl1, stage=stage+1)
rs = randscrambler(sl2, sl1, stage=stage + 1)
for i in range(N):
j, k = randOthers(i, N)
i2[i] = xor(ol[i], sl2[i], sl2[j], sl2[k])
@ -58,6 +58,7 @@ def randscrambler(ol, il, stage=0):
i1[i] = xor(ol[i], il[i], il[j], il[k])
return i1
@block
def randscrambler_top(o7, o6, o5, o4, o3, o2, o1, o0,
i7, i6, i5, i4, i3, i2, i1, i0):
@ -66,10 +67,12 @@ def randscrambler_top(o7, o6, o5, o4, o3, o2, o1, o0,
rs = randscrambler(sl2, sl1, stage=0)
return rs
o7, o6, o5, o4, o3, o2, o1, o0 = [Signal(bool()) for i in range(N)]
i7, i6, i5, i4, i3, i2, i1, i0 = [Signal(bool()) for i in range(N)]
v7, v6, v5, v4, v3, v2, v1, v0 = [Signal(bool()) for i in range(N)]
@block
def randscramblerBench():
@ -81,13 +84,13 @@ def randscramblerBench():
a[:] += 97
i7.next = a[7]
i6.next = a[6]
i5.next = a[5]
i4.next = a[4]
i3.next = a[3]
i2.next = a[2]
i1.next = a[1]
i0.next = a[0]
i6.next = a[6]
i5.next = a[5]
i4.next = a[4]
i3.next = a[3]
i2.next = a[2]
i1.next = a[1]
i0.next = a[0]
yield delay(10)
z[7] = o7
z[6] = o6
@ -107,5 +110,6 @@ def randscramblerBench():
return rs, stimulus
def test_randscramber():
assert conversion.verify(randscramblerBench()) == 0

37
myhdl/test/conversion/general/test_rom.py
View File

@ -2,43 +2,45 @@ import os
path = os.path
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always_comb,
instance, StopSimulation, conversion
)
D = 256
ROM = tuple([randrange(D) for i in range(D)])
ROM = tuple([randrange(D) for __ in range(D)])
@block
def rom1(dout, addr, clk):
@instance
def rdLogic() :
def rdLogic():
while 1:
yield clk.posedge
dout.next = ROM[int(addr)]
return rdLogic
@block
def rom2(dout, addr, clk):
theROM = ROM
@instance
def rdLogic() :
def rdLogic():
while 1:
yield clk.posedge
dout.next = theROM[int(addr)]
return rdLogic
@block
def rom3(dout, addr, clk):
@instance
def rdLogic() :
def rdLogic():
tmp = intbv(0)[8:]
while 1:
yield addr
@ -47,6 +49,7 @@ def rom3(dout, addr, clk):
return rdLogic
@block
def rom4(dout, addr, clk):
@ -56,7 +59,7 @@ def rom4(dout, addr, clk):
return read
@block
def RomBench(rom):
@ -87,19 +90,19 @@ def RomBench(rom):
return clkgen, stimulus, rom_inst
def test1():
assert conversion.verify(RomBench(rom1)) == 0
def test2():
assert conversion.verify(RomBench(rom2)) == 0
def test3():
assert conversion.verify(RomBench(rom3)) == 0
def test4():
assert conversion.verify(RomBench(rom4)) == 0

21
myhdl/test/conversion/general/test_set_dir.py
View File

@ -1,13 +1,14 @@
import os
import myhdl
from myhdl import *
from tempfile import mkdtemp
from shutil import rmtree
import myhdl
_version = myhdl.__version__.replace('.','')
_shortversion = _version.replace('dev','')
from myhdl import (block, Signal, intbv, always, toVHDL, toVerilog)
from myhdl import __version__
_version = __version__.replace('.', '')
_shortversion = _version.replace('dev', '')
@block
def simple_dir_model(din, dout, clk):
@ -18,14 +19,14 @@ def simple_dir_model(din, dout, clk):
dout.next = din
return register
def test_toVHDL_set_dir():
'''In order that a developer can define where in the project
hierarchy any generated VHDL files should be placed, it should be
possible to set a directory attribute on toVHDL controlling this.
'''
tmp_dir = mkdtemp()
din = Signal(intbv(0)[5:])
@ -39,9 +40,10 @@ def test_toVHDL_set_dir():
assert os.path.exists(os.path.join(tmp_dir, 'simple_dir_model.vhd'))
finally:
toVHDL.directory = None
toVHDL.directory = None
rmtree(tmp_dir)
def test_toVHDL_myhdl_package_set_dir():
'''In order that the MyHDL package files are located in the
same place as the generated VHDL files, when the directory attribute of
@ -67,6 +69,7 @@ def test_toVHDL_myhdl_package_set_dir():
rmtree(tmp_dir)
def test_toVerilog_set_dir():
'''In order that a developer can define where in the project
hierarchy any generated Verilog files should be placed, it should be
@ -107,7 +110,7 @@ def test_toVerilog_testbench_set_dir():
dout = Signal(intbv(0)[5:])
clock = Signal(bool(0))
no_testbench_state = toVerilog.no_testbench
no_testbench_state = toVerilog.no_testbench
toVerilog.no_testbench = False
try:

11
myhdl/test/conversion/general/test_ternary.py
View File

@ -1,9 +1,11 @@
import os
path = os.path
import unittest
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always_comb,
always, instance, StopSimulation,
conversion, toVHDL
)
@block
def ternary1(dout, clk, rst):
@ -36,6 +38,7 @@ def ternary2(dout, clk, rst):
return logic, comb
@block
def TernaryBench(ternary):
@ -67,12 +70,12 @@ def TernaryBench(ternary):
return stimulus, ternary_inst
# uncomment when we have a VHDL-2008 compliant simulator
def test_ternary1():
toVHDL.name = 'ternary1'
assert conversion.verify(TernaryBench(ternary1)) == 0
def test_ternary2():
toVHDL.name = 'ternary2'
assert conversion.verify(TernaryBench(ternary2)) == 0

26
myhdl/test/conversion/general/test_toplevel_method.py
View File

@ -1,10 +1,10 @@
import sys
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, always_comb, always)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
class HdlObj(object):
def __init__(self):
pass
@ -12,6 +12,7 @@ class HdlObj(object):
def method_func(self, clk, srst, x, y):
z = Signal(intbv(0, min=y.min, max=y.max))
ifx = self._mfunc(x, z)
@always(clk.posedge)
def hdl():
if srst:
@ -23,19 +24,26 @@ class HdlObj(object):
@block
def _mfunc(self, x, y):
@always_comb
def _hdl():
y.next = x + 1
return _hdl
@block
def _func(x,y):
def _func(x, y):
@always_comb
def _hdl():
y.next = x + 1
return _hdl
class HdlObjObj(object):
def __init__(self):
pass
@ -56,7 +64,9 @@ class HdlObjObj(object):
return hdl, ifx1, ifx2
class HdlObjAttrSimple(object):
def __init__(self):
self.Constant = 3
@ -66,17 +76,20 @@ class HdlObjAttrSimple(object):
# limitation for class method conversion, the object attributes
# can only be used/accessed during elaboration.
Constant = int(self.Constant)
@always(clk.posedge)
def hdl():
if srst:
y.next = 0
else:
y.next = x + (x+1) + Constant - 3
y.next = x + (x + 1) + Constant - 3
return hdl
class HdlObjNotSelf(object):
''' testing against using 'this' iso 'self '''
def __init__(this):
pass
@ -101,6 +114,7 @@ def test_hdlobj():
hdlobj_inst = HdlObj()
hdlobj_inst.method_func(clk, srst, x, y).analyze_convert()
def test_hdlobjobj():
clk = Signal(False)
srst = Signal(False)
@ -109,6 +123,7 @@ def test_hdlobjobj():
hdlobj_inst = HdlObjObj()
hdlobj_inst.method_func(clk, srst, x, y).analyze_convert()
def test_hdlobjattrsimple():
clk = Signal(False)
srst = Signal(False)
@ -117,6 +132,7 @@ def test_hdlobjattrsimple():
hdlobj_inst = HdlObjAttrSimple()
hdlobj_inst.method_func(clk, x, srst, y).analyze_convert()
def test_hdlobjnotself():
clk = Signal(False)
srst = Signal(False)

110
myhdl/test/conversion/general/test_unaryop.py
View File

@ -1,70 +1,73 @@
from myhdl import *
from myhdl import (block, Signal, modbv, delay, always_comb,
instance, StopSimulation, instances
)
import pytest
@block
def notVector0(
a,
z,
):
@always_comb
def outputs():
z.next = a & ~0x1
z.next = a & ~0x1
return instances()
@block
def notVector1(
a,
b,
z,
):
@always_comb
def outputs():
z.next = a & ~b
z.next = a & ~b
return instances()
@block
def notVector2(
a,
z,
):
@always_comb
def outputs():
z.next = a & +0xfe
z.next = a & +0xfe
return instances()
@block
def notVector3(
a,
b,
z,
):
@always_comb
def outputs():
z.next = a & +b
z.next = a & +b
return instances()
@block
def notVector4(
a,
z,
):
@always_comb
def outputs():
z.next = a & -0x2
z.next = a & -0x2
return instances()
@ -72,15 +75,15 @@ def notVector4(
@block
def notVectorBench0(rev=0):
clk = Signal(bool(0))
a = Signal(modbv(0)[8:])
b = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
clk = Signal(bool(0))
a = Signal(modbv(0)[8:])
b = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
@instance
def clkgen():
clk.next = 1
for i in range(400):
for dummy in range(400):
yield delay(10)
clk.next = not clk
@ -106,7 +109,6 @@ def notVectorBench0(rev=0):
a.next = 0xff
yield clk.posedge
raise StopSimulation
@instance
@ -124,7 +126,7 @@ def notVectorBench0(rev=0):
yield clk.posedge
assert z == 0xfe
yield clk.posedge
if 1 == rev:
i_notVector = notVector1(a, b, z)
elif 2 == rev:
@ -136,19 +138,19 @@ def notVectorBench0(rev=0):
else:
i_notVector = notVector0(a, z)
return i_notVector
return instances()
def test_notVector0():
sim = notVectorBench0(0)
sim.run_sim()
def test_notVector0Inst():
clk = Signal(bool(0))
a = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
a = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
i_dut = notVector0(a, z)
assert i_dut.analyze_convert() == 0
@ -157,19 +159,20 @@ def test_notVector0Inst():
def test_notVector0_convert():
i_dut = notVectorBench0(0)
assert i_dut.analyze_convert() == 0
#assert i_dut.verify_convert() == 0
# assert i_dut.verify_convert() == 0
def test_notVector1():
sim = notVectorBench0(1)
sim.run_sim()
def test_notVector1Inst():
clk = Signal(bool(0))
a = Signal(modbv(0)[8:])
b = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
a = Signal(modbv(0)[8:])
b = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
i_dut = notVector1(a, b, z)
assert i_dut.analyze_convert() == 0
@ -177,18 +180,19 @@ def test_notVector1Inst():
def test_notVector1_convert():
i_dut = notVectorBench0(1)
assert i_dut.analyze_convert() == 0
#assert i_dut.verify_convert() == 0
# assert i_dut.verify_convert() == 0
def test_notVector2():
sim = notVectorBench0(2)
sim.run_sim()
def test_notVector2Inst():
clk = Signal(bool(0))
a = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
a = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
i_dut = notVector2(a, z)
assert i_dut.analyze_convert() == 0
@ -197,19 +201,20 @@ def test_notVector2Inst():
def test_notVector2_convert():
i_dut = notVectorBench0(2)
assert i_dut.analyze_convert() == 0
#assert i_dut.verify_convert() == 0
# assert i_dut.verify_convert() == 0
def test_notVector3():
sim = notVectorBench0(3)
sim.run_sim()
def test_notVector3Inst():
clk = Signal(bool(0))
a = Signal(modbv(0)[8:])
b = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
a = Signal(modbv(0)[8:])
b = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
i_dut = notVector3(a, b, z)
assert i_dut.analyze_convert() == 0
@ -217,18 +222,19 @@ def test_notVector3Inst():
def test_notVector3_convert():
i_dut = notVectorBench0(3)
assert i_dut.analyze_convert() == 0
#assert i_dut.verify_convert() == 0
# assert i_dut.verify_convert() == 0
def test_notVector4():
sim = notVectorBench0(4)
sim.run_sim()
def test_notVector4Inst():
clk = Signal(bool(0))
a = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
a = Signal(modbv(0)[8:])
z = Signal(modbv(0)[8:])
i_dut = notVector4(a, z)
assert i_dut.analyze_convert() == 0
@ -237,5 +243,5 @@ def test_notVector4Inst():
def test_notVector4_convert():
i_dut = notVectorBench0(4)
assert i_dut.analyze_convert() == 0
#assert i_dut.verify_convert() == 0
# assert i_dut.verify_convert() == 0

52
myhdl/test/conversion/toVHDL/test_custom.py
View File

@ -5,15 +5,14 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance,
always, always_comb, StopSimulation, conversion)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def incRef(count, enable, clock, reset, n):
""" Incrementer with enable.
@ -24,6 +23,7 @@ def incRef(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@instance
def logic():
while 1:
@ -33,12 +33,14 @@ def incRef(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@block
def incGen(count, enable, clock, reset, n):
""" Generator with vhdl_code is not permitted """
@instance
def logic():
incGen.vhdl_code = "Template string"
@ -49,6 +51,7 @@ def incGen(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@ -62,6 +65,7 @@ def inc(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@always(clock.posedge, reset.negedge)
def incProcess():
# make it fail in conversion
@ -90,7 +94,6 @@ end process;
return incProcess
@block
def incErr(count, enable, clock, reset, n):
@ -123,7 +126,6 @@ end
return incProcess
@block
def inc_comb(nextCount, count, n):
@ -135,13 +137,14 @@ def inc_comb(nextCount, count, n):
nextCount.driven = "wire"
inc_comb.vhdl_code =\
inc_comb.vhdl_code = \
"""
$nextCount <= ($count + 1) mod $n;
"""
return logic
@block
def inc_seq(count, nextCount, enable, clock, reset):
@ -172,6 +175,7 @@ end process;
return logic
@block
def inc2(count, enable, clock, reset, n):
@ -188,7 +192,9 @@ def inc3(count, enable, clock, reset, n):
inc2_inst = inc2(count, enable, clock, reset, n)
return inc2_inst
class ClassIncrementer(object):
@block
def inc(self, count, enable, clock, reset, n):
""" Incrementer with enable.
@ -199,6 +205,7 @@ class ClassIncrementer(object):
reset -- asynchronous reset input
n -- counter max value
"""
@always(clock.posedge, reset.negedge)
def incProcess():
# make it fail in conversion
@ -229,20 +236,25 @@ class ClassIncrementer(object):
@block
def clockGen(clock):
@instance
def logic():
clock.next = 1
while 1:
yield delay(10)
clock.next = not clock
return logic
NRTESTS = 1000
ENABLES = tuple([min(1, randrange(5)) for i in range(NRTESTS)])
@block
def stimulus(enable, clock, reset):
@instance
def logic():
reset.next = INACTIVE_HIGH
@ -257,11 +269,13 @@ def stimulus(enable, clock, reset):
enable.next = ENABLES[i]
yield clock.negedge
raise StopSimulation
return logic
@block
def check(count, enable, clock, reset, n):
@instance
def logic():
expect = 0
@ -276,8 +290,10 @@ def check(count, enable, clock, reset, n):
# print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
# assert count == expect
print(count)
return logic
@block
def customBench(inc):
@ -296,47 +312,41 @@ def customBench(inc):
return inc_inst, clk_1, st_1, ch_1
def testIncRef():
assert conversion.verify(customBench(incRef)) == 0
def testInc():
assert conversion.verify(customBench(inc)) == 0
def testInc2():
assert conversion.verify(customBench(inc2)) == 0
def testInc3():
assert conversion.verify(customBench(inc3)) == 0
def testIncGen():
try:
assert conversion.verify(customBench(incGen)) == 0
except ConversionError as e:
except ConversionError:
pass
else:
assert False
def testIncErr():
try:
assert conversion.verify(customBench(incErr)) == 0
except ConversionError as e:
except ConversionError:
pass
else:
assert False
def testMethodInc():
incrementer = ClassIncrementer()
assert conversion.verify(customBench(incrementer.inc)) == 0

24
myhdl/test/conversion/toVHDL/test_enum.py
View File

@ -1,9 +1,9 @@
import myhdl
from myhdl import *
from random import randrange
from myhdl import (block, Signal, enum, intbv, delay, instance,
instances, always_comb, StopSimulation)
bitwise_op = enum('BW_AND', 'BW_ANDN', 'BW_OR', 'BW_XOR')
def bitwise(a, b, op):
r = intbv(0)[8:]
if op == bitwise_op.BW_AND:
@ -15,19 +15,24 @@ def bitwise(a, b, op):
elif op == bitwise_op.BW_XOR:
r[:] = a ^ b
return r
@block
def LogicUnit(a, b, c, op):
@always_comb
def operate():
c.next = bitwise(a,b,op)
c.next = bitwise(a, b, op)
return operate
@block
def bench_enum():
clock = Signal(False)
a, b, c = [Signal(intbv(0)[8:]) for i in range(3)]
a, b, c = [Signal(intbv(0)[8:]) for _ in range(3)]
op = Signal(bitwise_op.BW_AND)
logic_unit = LogicUnit(a=a, b=b, c=c, op=op)
@instance
@ -51,19 +56,20 @@ def bench_enum():
op.next = bitwise_op.BW_ANDN
yield clock.posedge
print(c)
op.next = bitwise_op.BW_OR
yield clock.posedge
print(c)
op.next = bitwise_op.BW_XOR
yield clock.posedge
print(c)
raise StopSimulation
return instances()
def test_enum():
assert bench_enum().verify_convert() == 0

3
myhdl/test/conversion/toVHDL/test_keywords.py
View File

@ -1,5 +1,4 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, always, always_comb)
from myhdl import ToVHDLWarning
import pytest

12
myhdl/test/conversion/toVHDL/test_loops.py
View File

@ -2,14 +2,14 @@ import os
path = os.path
from random import randrange
import myhdl
from myhdl import *
from myhdl.conversion import verify, analyze
from myhdl import (block, Signal, intbv, delay, instance)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
@block
def ForLoopError1(a, out):
@instance
def logic():
while 1:
@ -19,8 +19,10 @@ def ForLoopError1(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def LoopBench(LoopTest):
@ -28,7 +30,7 @@ def LoopBench(LoopTest):
z = Signal(intbv(0)[16:])
looptest_inst = LoopTest(a, z)
data = tuple([randrange(2**min(i, 16)) for i in range(100)])
data = tuple([randrange(2 ** min(i, 16)) for i in range(100)])
@instance
def stimulus():
@ -47,6 +49,4 @@ def testForLoopError1():
assert e.kind == _error.Requirement
else:
assert False

66
myhdl/test/conversion/toVHDL/test_newcustom.py
View File

@ -5,15 +5,14 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance,
always, always_comb, StopSimulation)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def incRef(count, enable, clock, reset, n):
""" Incrementer with enable.
@ -24,6 +23,7 @@ def incRef(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@instance
def logic():
while 1:
@ -33,12 +33,14 @@ def incRef(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@block
def incGen(count, enable, clock, reset, n):
""" Generator with __vhdl__ is not permitted """
@instance
def logic():
incGen.vhdl_code = "Template string"
@ -49,9 +51,10 @@ def incGen(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@block
def inc(count, enable, clock, reset, n):
""" Incrementer with enable.
@ -62,6 +65,7 @@ def inc(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@always(clock.posedge, reset.negedge)
def incProcess():
# make it fail in conversion
@ -86,13 +90,13 @@ process ($clock, $reset) begin
end if;
end process;
"""
return incProcess
@block
def incErr(count, enable, clock, reset, n):
@always(clock.posedge, reset.negedge)
def incProcess():
# make it fail in conversion
@ -118,9 +122,8 @@ always @(posedge $clock, negedge $reset) begin
end
end
"""
return incProcess
return incProcess
@block
@ -134,13 +137,14 @@ def inc_comb(nextCount, count, n):
nextCount.driven = "wire"
inc_comb.vhdl_code =\
inc_comb.vhdl_code = \
"""
$nextCount <= ($count + 1) mod $n;
"""
return logic
@block
def inc_seq(count, nextCount, enable, clock, reset):
@ -166,12 +170,13 @@ process ($clock, $reset) begin
end if;
end process;
"""
return logic
@block
def inc2(count, enable, clock, reset, n):
nextCount = Signal(intbv(0, min=0, max=n))
comb = inc_comb(nextCount, count, n)
@ -188,20 +193,25 @@ def inc3(count, enable, clock, reset, n):
@block
def clockGen(clock):
@instance
def logic():
clock.next = 1
while 1:
yield delay(10)
clock.next = not clock
return logic
NRTESTS = 1000
ENABLES = tuple([min(1, randrange(5)) for i in range(NRTESTS)])
@block
def stimulus(enable, clock, reset):
@instance
def logic():
reset.next = INACTIVE_HIGH
@ -216,11 +226,13 @@ def stimulus(enable, clock, reset):
enable.next = ENABLES[i]
yield clock.negedge
raise StopSimulation
return logic
@block
def check(count, enable, clock, reset, n):
@instance
def logic():
expect = 0
@ -235,6 +247,7 @@ def check(count, enable, clock, reset, n):
# print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
# assert count == expect
print(count)
return logic
@ -256,45 +269,36 @@ def customBench(inc):
return inc_inst, clk_1, st_1, ch_1
def testIncRef():
assert customBench(incRef).verify_convert() == 0
def testInc():
assert customBench(inc).verify_convert() == 0
def testInc2():
assert customBench(inc2).verify_convert() == 0
def testInc3():
assert customBench(inc3).verify_convert() == 0
def testIncGen():
try:
assert customBench(incGen).verify_convert() == 0
except ConversionError as e:
except ConversionError:
pass
else:
assert False
def testIncErr():
try:
assert customBench(incErr).verify_convert() == 0
except ConversionError as e:
except ConversionError:
pass
else:
assert False

117
myhdl/test/conversion/toVHDL/test_ops.py
View File

@ -4,12 +4,11 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl.conversion import verify
from myhdl import (block, Signal, intbv, delay, instance, StopSimulation)
NRTESTS = 10
@block
def binaryOps(
Bitand,
@ -43,18 +42,18 @@ def binaryOps(
FloorDiv.next = 0
if right != 0:
FloorDiv.next = left // right
## if left < 256 and right < 40:
# # if left < 256 and right < 40:
LeftShift.next = 0
if left < 256 and right < 26: # fails in ghdl for > 26
if left < 256 and right < 26: # fails in ghdl for > 26
LeftShift.next = left << right
Modulo.next = 0
Modulo.next = 0
if right != 0:
Modulo.next = left % right
Mul.next = left * right
# Icarus doesn't support ** yet
#if left < 256 and right < 40:
# if left < 256 and right < 40:
# Pow.next = left ** right
## Pow.next = 0
# # Pow.next = 0
RightShift.next = left >> right
Sub.next = 0
if left >= right:
@ -68,17 +67,19 @@ def binaryOps(
GE.next = left >= right
Booland.next = bool(left) and bool(right)
Boolor.next = bool(left) or bool(right)
return logic
@block
def binaryBench(m, n):
M = 2**m
N = 2**n
M = 2 ** m
N = 2 ** n
P = min(M, N)
seqP = tuple(range(P))
seqM = tuple([randrange(M) for i in range(NRTESTS)])
seqN = tuple([randrange(N) for i in range(NRTESTS)])
seqM = tuple([randrange(M) for __ in range(NRTESTS)])
seqN = tuple([randrange(N) for __ in range(NRTESTS)])
left = Signal(intbv(0)[m:])
right = Signal(intbv(0)[n:])
@ -88,12 +89,12 @@ def binaryBench(m, n):
FloorDiv = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0)[64:])
Modulo = Signal(intbv(0)[m:])
Mul = Signal(intbv(0)[m+n:])
Mul = Signal(intbv(0)[m + n:])
Pow = Signal(intbv(0)[64:])
RightShift = Signal(intbv(0)[m:])
Sub = Signal(intbv(0)[max(m, n):])
Sum = Signal(intbv(0)[max(m, n)+1:])
EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
Sum = Signal(intbv(0)[max(m, n) + 1:])
EQ, NE, LT, GT, LE, GE = [Signal(bool()) for __ in range(6)]
Booland, Boolor = [Signal(bool()) for i in range(2)]
binops = binaryOps(Bitand,
@ -126,13 +127,13 @@ def binaryBench(m, n):
right.next = 0
yield delay(10)
left.next = 0
right.next = N-1
right.next = N - 1
yield delay(10)
left.next = M-1
left.next = M - 1
right.next = 0
yield delay(10)
left.next = M-1
right.next = N-1
left.next = M - 1
right.next = N - 1
for i in range(len(seqP)):
left.next = seqP[i]
right.next = seqP[i]
@ -143,7 +144,6 @@ def binaryBench(m, n):
yield delay(10)
# raise StopSimulation
@instance
def check():
while True:
@ -174,11 +174,13 @@ def binaryBench(m, n):
return binops, stimulus, check
def testBinary():
for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
# for m, n in ((2, 6),):
assert binaryBench(m, n).verify_convert() == 0
@block
def multiOps(
Bitand,
@ -187,6 +189,7 @@ def multiOps(
Booland,
Boolor,
argm, argn, argp):
@instance
def logic():
while 1:
@ -196,22 +199,22 @@ def multiOps(
Bitxor.next = argm ^ argn ^ argp
Booland.next = bool(argm) and bool(argn) and bool(argp)
Boolor.next = bool(argm) and bool(argn) and bool(argp)
return logic
return logic
@block
def multiBench(m, n, p):
M = 2**m
N = 2**n
P = 2**p
M = 2 ** m
N = 2 ** n
P = 2 ** p
Q = min(M, N, P)
seqQ = tuple(range(1, Q))
seqM = tuple([randrange(M) for i in range(NRTESTS)])
seqN = tuple([randrange(N) for i in range(NRTESTS)])
seqP = tuple([randrange(P) for i in range(NRTESTS)])
seqM = tuple([randrange(M) for __ in range(NRTESTS)])
seqN = tuple([randrange(N) for __ in range(NRTESTS)])
seqP = tuple([randrange(P) for __ in range(NRTESTS)])
argm = Signal(intbv(0)[m:])
argn = Signal(intbv(0)[n:])
@ -240,13 +243,13 @@ def multiBench(m, n, p):
argn.next = seqN[i]
argp.next = seqP[i]
yield delay(10)
## for j, k, l in ((0, 0, 0), (0, 0, P-1), (0, N-1, P-1),
## (M-1, 0, 0), (M-1, 0, P-1), (M-1, N-1, 0),
## (0, N-1, 0), (M-1, N-1, P-1)):
## argm.next = j
## argn.next = k
## argp.next = l
## yield delay(10)
# # for j, k, l in ((0, 0, 0), (0, 0, P-1), (0, N-1, P-1),
# # (M-1, 0, 0), (M-1, 0, P-1), (M-1, N-1, 0),
# # (0, N-1, 0), (M-1, N-1, P-1)):
# # argm.next = j
# # argn.next = k
# # argp.next = l
# # yield delay(10)
@instance
def check():
@ -262,10 +265,12 @@ def multiBench(m, n, p):
return multiops, stimulus, check
def testMultiOps():
for m, n, p in ((4, 4, 4,), (5, 3, 2), (3, 4, 6), (3, 7, 4)):
assert multiBench(m, n, p).verify_convert() == 0
@block
def unaryOps(
Not_kw,
@ -273,21 +278,24 @@ def unaryOps(
UnaryAdd,
UnarySub,
arg):
@instance
def logic():
while 1:
yield arg
Not_kw.next = not arg
Invert.next = ~arg
# unary operators not supported ?
#UnaryAdd.next = +arg
# UnaryAdd.next = +arg
# UnarySub.next = --arg
return logic
@block
def unaryBench(m):
M = 2**m
M = 2 ** m
seqM = tuple([randrange(M) for i in range(NRTESTS)])
arg = Signal(intbv(0)[m:])
@ -322,12 +330,14 @@ def unaryBench(m):
return unaryops, stimulus, check
def testUnaryOps():
for m in (4, 7):
assert unaryBench(m).verify_convert() == 0
@block
def augmOps( Bitand,
def augmOps(Bitand,
Bitor,
Bitxor,
FloorDiv,
@ -338,6 +348,7 @@ def augmOps( Bitand,
Sub,
Sum,
left, right):
@instance
def logic():
# var = intbv(0)[min(64, len(left) + len(right)):]
@ -383,16 +394,18 @@ def augmOps( Bitand,
var[:] = left
var >>= right
RightShift.next = var
return logic
@block
def augmBench(m, n):
M = 2**m
N = 2**n
seqM = tuple([randrange(M) for i in range(NRTESTS)])
seqN = tuple([randrange(N) for i in range(NRTESTS)])
M = 2 ** m
N = 2 ** n
seqM = tuple([randrange(M) for __ in range(NRTESTS)])
seqN = tuple([randrange(N) for __ in range(NRTESTS)])
left = Signal(intbv(0)[m:])
right = Signal(intbv(0)[n:])
@ -402,12 +415,12 @@ def augmBench(m, n):
FloorDiv = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0)[64:])
Modulo = Signal(intbv(0)[m:])
Mul = Signal(intbv(0)[m+n:])
Mul = Signal(intbv(0)[m + n:])
RightShift = Signal(intbv(0)[m:])
Sub = Signal(intbv(0)[max(m, n):])
Sum = Signal(intbv(0)[max(m, n)+1:])
Sum = Signal(intbv(0)[max(m, n) + 1:])
augmops = augmOps( Bitand,
augmops = augmOps(Bitand,
Bitor,
Bitxor,
FloorDiv,
@ -428,18 +441,17 @@ def augmBench(m, n):
right.next = 0
yield delay(10)
left.next = 0
right.next = N-1
right.next = N - 1
yield delay(10)
left.next = M-1
left.next = M - 1
right.next = 0
yield delay(10)
left.next = M-1
right.next = N-1
left.next = M - 1
right.next = N - 1
for i in range(NRTESTS):
left.next = seqM[i]
right.next = seqN[i]
yield delay(10)
@instance
def check():
@ -456,9 +468,10 @@ def augmBench(m, n):
print(Modulo)
print(Mul)
print(RightShift)
return augmops, stimulus, check
def testAugmOps():
for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
assert augmBench(m, n).verify_convert() == 0

273
myhdl/test/conversion/toVHDL/test_signed.py
View File

@ -1,26 +1,24 @@
import os
path = os.path
import random
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance, StopSimulation)
from myhdl.conversion import verify
import pytest
NRTESTS = 10
@block
def binaryOps(
Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
Modulo,
Mul,
## Pow,
# # Pow,
RightShift,
Sub,
Sum, Sum1, Sum2, Sum3,
@ -38,25 +36,25 @@ def binaryOps(
def logic():
while 1:
yield left, right, aBit
## Bitand.next = left & right
## Bitor.next = left | right
## Bitxor.next = left ^ right
## if right != 0:
## FloorDiv.next = left // right
# # Bitand.next = left & right
# # Bitor.next = left | right
# # Bitxor.next = left ^ right
# # if right != 0:
# # FloorDiv.next = left // right
# Keep left shifts smaller than 2** 31 for VHDL's to_integer
LeftShift.next = 0
if left < 256 and right < 22 and right >= 0:
LeftShift.next = left << right
## if right != 0:
## Modulo.next = left % right
# # if right != 0:
# # Modulo.next = left % right
Mul.next = left * right
## # Icarus doesn't support ** yet
## #if left < 256 and right < 22:
## # Pow.next = left ** right
## Pow.next = 0
## if right >= -0:
## RightShift.next = left >> right
## RightShift.next = left
# # # Icarus doesn't support ** yet
# # #if left < 256 and right < 22:
# # # Pow.next = left ** right
# # Pow.next = 0
# # if right >= -0:
# # RightShift.next = left >> right
# # RightShift.next = left
Sub.next = left - right
Sum.next = left + right
Sum1.next = left + right[2:]
@ -70,6 +68,7 @@ def binaryOps(
GE.next = left >= right
BoolAnd.next = bool(left) and bool(right)
BoolOr.next = bool(left) or bool(right)
return logic
@ -78,48 +77,47 @@ def binaryBench(Ll, Ml, Lr, Mr):
seqL = []
seqR = []
for i in range(NRTESTS):
for __ in range(NRTESTS):
seqL.append(randrange(Ll, Ml))
seqR.append(randrange(Lr, Mr))
for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
for j, k in ((Ll, Lr), (Ml - 1, Mr - 1), (Ll, Mr - 1), (Ml - 1, Lr)):
seqL.append(j)
seqR.append(k)
seqL = tuple(seqL)
seqR = tuple(seqR)
aBit = Signal(bool(0))
left = Signal(intbv(Ll, min=Ll, max=Ml))
right = Signal(intbv(Lr, min=Lr, max=Mr))
M = 2**14
Bitand = Signal(intbv(0, min=-2**17, max=2**17))
## Bitand_v = Signal(intbv(0, min=-2**17, max=2**17))
## Bitor = Signal(intbv(0)[max(m, n):])
## Bitor_v = Signal(intbv(0)[max(m, n):])
## Bitxor = Signal(intbv(0)[max(m, n):])
## Bitxor_v = Signal(intbv(0)[max(m, n):])
## FloorDiv = Signal(intbv(0)[m:])
## FloorDiv_v = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
M = 2 ** 14
Bitand = Signal(intbv(0, min=-2 ** 17, max=2 ** 17))
# # Bitand_v = Signal(intbv(0, min=-2**17, max=2**17))
# # Bitor = Signal(intbv(0)[max(m, n):])
# # Bitor_v = Signal(intbv(0)[max(m, n):])
# # Bitxor = Signal(intbv(0)[max(m, n):])
# # Bitxor_v = Signal(intbv(0)[max(m, n):])
# # FloorDiv = Signal(intbv(0)[m:])
# # FloorDiv_v = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0, min=-2 ** 64, max=2 ** 64))
Modulo = Signal(intbv(0)[M:])
Mul = Signal(intbv(0, min=-2**17, max=2**17))
## Pow = Signal(intbv(0)[64:])
Mul = Signal(intbv(0, min=-2 ** 17, max=2 ** 17))
# # Pow = Signal(intbv(0)[64:])
RightShift = Signal(intbv(0, min=-M, max=M))
Sub, Sub1, Sub2, Sub3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
BoolAnd, BoolOr = [Signal(bool()) for i in range(2)]
Sub = Signal(intbv(min=-M, max=M))
Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for __ in range(4)]
EQ, NE, LT, GT, LE, GE = [Signal(bool()) for __ in range(6)]
BoolAnd, BoolOr = [Signal(bool()) for __ in range(2)]
binops = binaryOps(
Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
Modulo,
Mul,
## Pow,
# # Pow,
RightShift,
Sub,
Sum, Sum1, Sum2, Sum3,
@ -133,7 +131,6 @@ def binaryBench(Ll, Ml, Lr, Mr):
BoolOr,
left, right, aBit)
@instance
def stimulus():
for i in range(len(seqL)):
@ -147,25 +144,25 @@ def binaryBench(Ll, Ml, Lr, Mr):
yield left, right
aBit.next = not aBit
yield delay(1)
#print "%s %s %s %s" % (left, right, Mul, Mul_v)
#print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v))
#print "%s %s %s %s" % (left, right, Sum, Sum_v)
#print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v))
## print left
## print right
## print bin(left)
## print bin(right)
## print bin(Bitand)
## print bin(Bitand_v)
## print Bitand
## print Bitand_v
## self.assertEqual(Bitand, Bitand_v)
#w = len(Bitand)
#self.assertEqual(bin(Bitand, w), bin(Bitand_v,w ))
## self.assertEqual(Bitor, Bitor_v)
## self.assertEqual(Bitxor, Bitxor_v)
## ## self.assertEqual(FloorDiv, FloorDiv_v)
# print "%s %s %s %s" % (left, right, Mul, Mul_v)
# print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v))
# print "%s %s %s %s" % (left, right, Sum, Sum_v)
# print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v))
# # print left
# # print right
# # print bin(left)
# # print bin(right)
# # print bin(Bitand)
# # print bin(Bitand_v)
# # print Bitand
# # print Bitand_v
# # self.assertEqual(Bitand, Bitand_v)
# w = len(Bitand)
# self.assertEqual(bin(Bitand, w), bin(Bitand_v,w ))
# # self.assertEqual(Bitor, Bitor_v)
# # self.assertEqual(Bitxor, Bitxor_v)
# # ## self.assertEqual(FloorDiv, FloorDiv_v)
print(LeftShift)
# print Modulo
print(Mul)
@ -186,7 +183,7 @@ def binaryBench(Ll, Ml, Lr, Mr):
print(int(BoolOr))
return binops, stimulus, check
@pytest.mark.filterwarnings("ignore:Signal is not driven")
def testBinaryOps():
@ -199,15 +196,17 @@ def testBinaryOps():
(-54, -20, 45, 73),
(-25, -12, -123, -66),
):
assert binaryBench(Ll, Ml, Lr, Mr ).verify_convert() == 0
assert binaryBench(Ll, Ml, Lr, Mr).verify_convert() == 0
@block
@block
def unaryOps(
BoolNot,
Invert,
UnaryAdd,
UnarySub,
arg):
@instance
def logic():
while 1:
@ -215,13 +214,15 @@ def unaryOps(
# BoolNot.next = not arg
Invert.next = ~arg
# UnaryAdd.next = +arg
UnarySub.next = --arg
UnarySub.next = - -arg
return logic
@block
def unaryBench( m):
M = 2**m
@block
def unaryBench(m):
M = 2 ** m
seqM = tuple([i for i in range(-M, M)])
arg = Signal(intbv(0, min=-M, max=+M))
@ -254,59 +255,59 @@ def unaryBench( m):
# print UnaryAdd
print(UnarySub)
return unaryops, stimulus, check
def testUnaryOps():
for m in (4, 7):
assert unaryBench(m).verify_convert() == 0
@block
def augmOps(
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
# # Bitand,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
## Modulo,
# # Modulo,
Mul,
RightShift,
Sub,
Sum,
left, right):
M = 2**17
N = 2**64
M = 2 ** 17
N = 2 ** 64
@instance
def logic():
var = intbv(0, min=-M, max=+M)
var2 = intbv(0, min=-N, max=+N)
while 1:
yield left, right
## var[:] = left
## var &= right
## Bitand.next = var
## var[:] = left
## var |= right
## Bitor.next = var
## var[:] = left
## var ^= left
## Bitxor.next = var
## if right != 0:
## var[:] = left
## var //= right
## FloorDiv.next = var
# # var[:] = left
# # var &= right
# # Bitand.next = var
# # var[:] = left
# # var |= right
# # Bitor.next = var
# # var[:] = left
# # var ^= left
# # Bitxor.next = var
# # if right != 0:
# # var[:] = left
# # var //= right
# # FloorDiv.next = var
LeftShift.next = 0
if left < 256 and right < 22 and right >= 0:
var2[:] = left
var2 <<= right
LeftShift.next = var2
## if right != 0:
## var[:] = left
## var %= right
## Modulo.next = var
# # if right != 0:
# # var[:] = left
# # var %= right
# # Modulo.next = var
var[:] = left
var *= right
Mul.next = var
@ -328,47 +329,46 @@ def augmOps(
@block
def augmBench( Ll, Ml, Lr, Mr):
M = 2**17
def augmBench(Ll, Ml, Lr, Mr):
M = 2 ** 17
seqL = []
seqR = []
for i in range(NRTESTS):
seqL.append(randrange(Ll, Ml))
seqR.append(randrange(Lr, Mr))
for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
for j, k in ((Ll, Lr), (Ml - 1, Mr - 1), (Ll, Mr - 1), (Ml - 1, Lr)):
seqL.append(j)
seqR.append(k)
seqL = tuple(seqL)
seqR = tuple(seqR)
left = Signal(intbv(Ll, min=Ll, max=Ml))
right = Signal(intbv(Lr, min=Lr, max=Mr))
## Bitand = Signal(intbv(0)[max(m, n):])
## Bitor = Signal(intbv(0)[max(m, n):])
## Bitxor = Signal(intbv(0)[max(m, n):])
## FloorDiv = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
## Modulo = Signal(intbv(0)[m:])
# # Bitand = Signal(intbv(0)[max(m, n):])
# # Bitor = Signal(intbv(0)[max(m, n):])
# # Bitxor = Signal(intbv(0)[max(m, n):])
# # FloorDiv = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0, min=-2 ** 64, max=2 ** 64))
# # Modulo = Signal(intbv(0)[m:])
Mul = Signal(intbv(0, min=-M, max=+M))
RightShift = Signal(intbv(0, min=-M, max=+M))
Sub = Signal(intbv(0, min=-M, max=+M))
Sum = Signal(intbv(0, min=-M, max=+M))
augmops = augmOps(
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
# # Bitand,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
## Modulo,
# # Modulo,
Mul,
RightShift,
Sub,
@ -381,29 +381,31 @@ def augmBench( Ll, Ml, Lr, Mr):
left.next = seqL[i]
right.next = seqR[i]
yield delay(10)
@instance
def check():
while 1:
yield left, right
yield delay(1)
# print "%s %s %s %s" % (left, right, Or, Or_v)
## self.assertEqual(Bitand, Bitand_v)
## self.assertEqual(Bitor, Bitor_v)
## self.assertEqual(Bitxor, Bitxor_v)
## self.assertEqual(FloorDiv, FloorDiv_v)
# # self.assertEqual(Bitand, Bitand_v)
# # self.assertEqual(Bitor, Bitor_v)
# # self.assertEqual(Bitxor, Bitxor_v)
# # self.assertEqual(FloorDiv, FloorDiv_v)
print(LeftShift)
## self.assertEqual(Modulo, Modulo_v)
# # self.assertEqual(Modulo, Modulo_v)
print(Mul)
print(RightShift)
print(Sub)
print(Sum)
return augmops, stimulus, check
def checkAugmOps( Ll, Ml, Lr, Mr):
return augmops, stimulus, check
def checkAugmOps(Ll, Ml, Lr, Mr):
assert verify(augmBench, Ll, Ml, Lr, Mr) == 0
def testAugmOps():
for Ll, Ml, Lr, Mr in (
(-254, 236, 0, 4),
@ -416,11 +418,11 @@ def testAugmOps():
):
assert augmBench(Ll, Ml, Lr, Mr).verify_convert() == 0
@block
def expressions(a, b, clk):
c = Signal(intbv(0, min=0, max=47))
e = Signal(bool())
@instance
def logic():
@ -442,8 +444,8 @@ def expressions(a, b, clk):
a.next = d + c
b.next = d >= c
yield clk.posedge
## a.next = d & c
## b.next = c + (d & c)
# # a.next = d & c
# # b.next = c + (d & c)
yield clk.posedge
a.next = d + -c
b.next = c + (-d)
@ -459,12 +461,12 @@ def expressions(a, b, clk):
yield clk.posedge
a.next = ~c + 1
b.next = ~d + 1
yield clk.posedge
raise StopSimulation
return logic
@block
def expressionsBench():
@ -495,6 +497,3 @@ def expressionsBench():
def testExpressions():
assert expressionsBench().verify_convert() == 0

41
myhdl/test/conversion/toVerilog/test_GrayInc.py
View File

@ -3,8 +3,9 @@ path = os.path
import unittest
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always,
StopSimulation, negedge)
from myhdl._Simulation import Simulation
from .test_bin2gray import bin2gray
from .test_inc import inc
@ -13,27 +14,29 @@ from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def GrayInc_0(graycnt, enable, clock, reset, width):
bincnt = Signal(intbv(0)[width:])
inc_1 = inc(bincnt, enable, clock, reset, n=2**width)
inc_1 = inc(bincnt, enable, clock, reset, n=2 ** width)
bin2gray_1 = bin2gray(B=bincnt, G=graycnt, width=width)
return inc_1, bin2gray_1
@block
def GrayIncReg_0(graycnt, enable, clock, reset, width):
graycnt_comb = Signal(intbv(0)[width:])
gray_inc_1 = GrayInc_0(graycnt_comb, enable, clock, reset, width)
@always(clock.posedge)
def reg_1():
graycnt.next = graycnt_comb
return gray_inc_1, reg_1
@ -42,11 +45,14 @@ graycnt = Signal(intbv(0)[width:])
enable, clock, reset = [Signal(bool()) for i in range(3)]
# GrayIncReg(graycnt, enable, clock, reset, width)
def GrayIncReg_v(name, graycnt, enable, clock, reset, width):
return setupCosimulation(**locals())
graycnt_v = Signal(intbv(0)[width:])
class TestGrayInc(unittest.TestCase):
def clockGen(self):
@ -74,7 +80,7 @@ class TestGrayInc(unittest.TestCase):
yield delay(1)
# print "%d graycnt %s %s" % (now(), graycnt, graycnt_v)
self.assertEqual(graycnt, graycnt_v)
def bench(self):
gray_inc_reg_1 = GrayIncReg_0(graycnt, enable, clock, reset, width).convert(hdl='Verilog')
gray_inc_reg_v = GrayIncReg_v(GrayIncReg_0.__name__, graycnt_v, enable, clock, reset, width)
@ -88,19 +94,4 @@ class TestGrayInc(unittest.TestCase):
""" Check gray inc operation """
sim = self.bench()
sim.run(quiet=1)

219
myhdl/test/conversion/toVerilog/test_NotSupported.py
View File

@ -1,12 +1,11 @@
import os
path = os.path
import unittest
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, instance)
from myhdl import ConversionError
from myhdl.conversion._misc import _error
class TestNotSupported(unittest.TestCase):
def check(self, *args):
@ -19,215 +18,252 @@ class TestNotSupported(unittest.TestCase):
def nocheck(self, *args):
args[0](*args[1:]).convert(hdl='Verilog')
def testAssList(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
[p, q] = 1, 2
return logic
self.check(g, z, a)
def testAssTuple(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
p, q = 1, 2
return logic
self.check(g, z, a)
def testClass(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
class c:
pass
return logic
self.check(g, z, a)
return logic
self.check(g, z, a)
def testDict(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
d = {}
return logic
self.check(g, z, a)
def testDiv(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = z / a
return logic
self.check(g, z, a)
def testFrom(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
from os import path
return logic
self.check(g, z, a)
def testFunction(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
def f():
pass
return logic
self.check(g, z, a)
def testGlobal(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
global e
return logic
self.check(g, z, a)
def testImport(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
import os
return logic
self.check(g, z, a)
def testLambda(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
lambda: 1
return logic
self.check(g, z, a)
def testListCompIf(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
l = [i for i in range(5) if i > 1]
return logic
self.check(g, z, a)
def testList(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
l = [1, 2, 3]
return logic
self.check(g, z, a)
## def testPower(self):
## a = Signal(bool())
## z = Signal(bool())
## def g(z, a):
## while 1:
## yield a
## z.next = 2 ** 8
## self.check(g, z, a)
# # def testPower(self):
# # a = Signal(bool())
# # z = Signal(bool())
# # def g(z, a):
# # while 1:
# # yield a
# # z.next = 2 ** 8
# # self.check(g, z, a)
## def testReturn(self):
## a = Signal(bool())
## z = Signal(bool())
## def g(z, a):
## while 1:
## yield a
## z.next = 1
## return
## self.check(g, z, a)
# # def testReturn(self):
# # a = Signal(bool())
# # z = Signal(bool())
# # def g(z, a):
# # while 1:
# # yield a
# # z.next = 1
# # return
# # self.check(g, z, a)
def testTryExcept(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
@ -237,15 +273,18 @@ class TestNotSupported(unittest.TestCase):
pass
except:
pass
return logic
self.check(g, z, a)
def testTryFinally(self):
a = Signal(bool())
z = Signal(bool())
@block
def g(z, a):
@instance
def logic():
while 1:
@ -255,54 +294,60 @@ class TestNotSupported(unittest.TestCase):
pass
finally:
pass
return logic
self.check(g, z, a)
def testChainedCompare(self):
a, b, c = [Signal(bool()) for i in range(3)]
z = Signal(bool())
@block
def g(z, a, b, c):
@instance
def logic():
while 1:
yield a, b, c
z.next = a <= b < c
return logic
self.check(g, z, a, b, c)
## def testShortcutAnd(self):
## a, b = [Signal(bool()) for i in range(2)]
## z = Signal(bool())
## def g(z, a, b):
## while 1:
## yield a
## if a:
## pass
## else:
## z.next = a and b
## self.check(g, z, a, b)
# # def testShortcutAnd(self):
# # a, b = [Signal(bool()) for i in range(2)]
# # z = Signal(bool())
# # def g(z, a, b):
# # while 1:
# # yield a
# # if a:
# # pass
# # else:
# # z.next = a and b
# # self.check(g, z, a, b)
## def testShortcutOr(self):
## a, b, c = [Signal(bool()) for i in range(3)]
## z = Signal(bool())
## def g(z, a, b):
## while 1:
## yield a
## if a:
## pass
## else:
## z.next = a < (b or c)
## self.check(g, z, a, b)
# # def testShortcutOr(self):
# # a, b, c = [Signal(bool()) for i in range(3)]
# # z = Signal(bool())
# # def g(z, a, b):
# # while 1:
# # yield a
# # if a:
# # pass
# # else:
# # z.next = a < (b or c)
# # self.check(g, z, a, b)
def testNonBoolArgAnd(self):
a = Signal(bool())
b = intbv(0)[2:]
z = Signal(bool())
@block
def g(z, a, b):
@instance
def logic():
while 1:
@ -311,7 +356,9 @@ class TestNotSupported(unittest.TestCase):
pass
else:
z.next = a and b
return logic
self.check(g, z, a, b)
def testNonBoolArgOr(self):
@ -319,9 +366,10 @@ class TestNotSupported(unittest.TestCase):
b = intbv(0)[2:]
c = Signal(bool())
z = Signal(bool())
@block
def g(z, a, b):
@instance
def logic():
while 1:
@ -330,91 +378,104 @@ class TestNotSupported(unittest.TestCase):
pass
else:
z.next = a < (b or c)
return logic
self.check(g, z, a, b)
def testExtraArguments(self):
a, b, c = [Signal(bool()) for i in range(3)]
c = [1, 2]
def g(a, *args):
return a
@block
def f(a, b, c, *args):
@instance
def logic():
g(a, b)
yield a
return logic
self.check(f, a, b, c)
def testExtraPositionalArgsInCall(self):
a, b, c = [Signal(bool()) for i in range(3)]
a, b, c = [Signal(bool()) for __ in range(3)]
c = [1]
d = {'b':2}
def h(b):
return b
@block
def g(a):
@instance
def logic():
h(*c)
yield a
return logic
@block
def f(a, b, c):
return g(a)
x = self.check(f, a, b, c)
def testExtraNamedArgsInCall(self):
a, b, c = [Signal(bool()) for i in range(3)]
a, b, c = [Signal(bool()) for __ in range(3)]
c = [1]
d = {'b':2}
def h(b):
return b
@block
def g(a):
@instance
def logic():
h(**d)
yield a
return logic
@block
def f(a, b, c):
return g(a)
x = self.check(f, a, b, c)
class TestMisc(unittest.TestCase):
def test(self):
a, b, c = [Signal(bool()) for i in range(3)]
a, b, c = [Signal(bool()) for __ in range(3)]
c = [1]
d = {'a':2}
def h(b):
return b
@block
def g(a):
@instance
def logic():
h(a)
yield a
return logic
# b and c are not being used
@block
def f(a, b, c):
return g(a)
f(a, b, c)
x = f(a, b, c).convert(hdl='Verilog')

73
myhdl/test/conversion/toVerilog/test_RandomScrambler.py
View File

@ -5,32 +5,36 @@ from unittest import TestCase
import random
from random import randrange
random.seed(2)
import time
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance, toVerilog)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
N = 8
M = 2 ** N
DEPTH = 5
@block
def XorGate(z, a, b, c):
@instance
def logic():
while 1:
yield a, b, c
z.next = a ^ b ^ c
return logic
def randOthers(i, n):
l = list(range(n))
l.remove(i)
random.shuffle(l)
return l[0], l[1]
@block
def RandomScramblerModule(ol, il, stage=0):
""" Recursive hierarchy of random xor gates.
@ -39,8 +43,8 @@ def RandomScramblerModule(ol, il, stage=0):
"""
sl1 = [Signal(bool()) for i in range(N)]
sl2 = [Signal(bool()) for i in range(N)]
sl1 = [Signal(bool()) for __ in range(N)]
sl2 = [Signal(bool()) for __ in range(N)]
i1 = [None] * N
i2 = [None] * N
@ -48,7 +52,7 @@ def RandomScramblerModule(ol, il, stage=0):
for i in range(N):
j, k = randOthers(i, N)
i1[i] = XorGate(sl1[i], il[i], il[j], il[k])
rs = RandomScramblerModule(sl2, sl1, stage=stage+1)
rs = RandomScramblerModule(sl2, sl1, stage=stage + 1)
for i in range(N):
j, k = randOthers(i, N)
i2[i] = XorGate(ol[i], sl2[i], sl2[j], sl2[k])
@ -58,21 +62,22 @@ def RandomScramblerModule(ol, il, stage=0):
j, k = randOthers(i, N)
i1[i] = XorGate(ol[i], il[i], il[j], il[k])
return i1
@block
def RandomScrambler(o7, o6, o5, o4, o3, o2, o1, o0,
i7, i6, i5, i4, i3, i2, i1, i0):
sl1 = [i7, i6, i5, i4, i3, i2, i1, i0]
sl2 = [o7, o6, o5, o4, o3, o2, o1, o0]
sl2 = [o7, o6, o5, o4, o3, o2, o1, o0]
rs = RandomScramblerModule(sl2, sl1, stage=0)
return rs
o7, o6, o5, o4, o3, o2, o1, o0 = [Signal(bool()) for i in range(N)]
i7, i6, i5, i4, i3, i2, i1, i0 = [Signal(bool()) for i in range(N)]
v7, v6, v5, v4, v3, v2, v1, v0 = [Signal(bool()) for i in range(N)]
def RandomScrambler_v(name,
o7, o6, o5, o4, o3, o2, o1, o0,
i7, i6, i5, i4, i3, i2, i1, i0):
@ -82,20 +87,20 @@ def RandomScrambler_v(name,
class TestRandomScrambler(TestCase):
def stimulus(self):
input = intbv(0)
tinput = intbv(0)
output = intbv(0)
output_v = intbv(0)
for i in range(100):
# while 1:
input[:] = randrange(M)
i7.next = input[7]
i6.next = input[6]
i5.next = input[5]
i4.next = input[4]
i3.next = input[3]
i2.next = input[2]
i1.next = input[1]
i0.next = input[0]
tinput[:] = randrange(M)
i7.next = tinput[7]
i6.next = tinput[6]
i5.next = tinput[5]
i4.next = tinput[4]
i3.next = tinput[3]
i2.next = tinput[2]
i1.next = tinput[1]
i0.next = tinput[0]
yield delay(10)
output[7] = o7
output[6] = o6
@ -113,14 +118,13 @@ class TestRandomScrambler(TestCase):
output_v[2] = o2
output_v[1] = o1
output_v[0] = o0
## print output
## print output_v
## print input
# # print output
# # print output_v
# # print input
self.assertEqual(output, output_v)
def test(self):
rs = toVerilog(RandomScrambler(
rs = toVerilog(RandomScrambler(
o7, o6, o5, o4, o3, o2, o1, o0,
i7, i6, i5, i4, i3, i2, i1, i0
))
@ -132,20 +136,7 @@ class TestRandomScrambler(TestCase):
sim = Simulation(rs, self.stimulus(), rs_v)
sim.run()
if __name__ == '__main__':
unittest.main()

47
myhdl/test/conversion/toVerilog/test_always_comb.py
View File

@ -18,69 +18,80 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
""" Run the unit tests for always_comb """
import random
from random import randrange
# random.seed(3) # random, but deterministic
import os
from os import path
from random import seed, shuffle
seed('We want repeatable randomness') # random, but deterministic
import unittest
from unittest import TestCase
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always_comb, StopSimulation,)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
QUIET = 1
@block
def design1(a, b, c, d, p, q, r):
def logic():
p.next = a | b
return always_comb(logic)
@block
def design2(a, b, c, d, p, q, r):
def logic():
p.next = a | b
q.next = c & d
r.next = a ^ c
return always_comb(logic)
@block
def design3(a, b, c, d, p, q, r):
def logic():
if a:
p.next = c | b
q.next = c & d
r.next = d ^ c
return always_comb(logic)
@block
def design4(a, b, c, d, p, q, r):
def logic():
p.next = a | b
q.next = c & d
r.next = a ^ c
q.next = c | d
return always_comb(logic)
@block
def design5(a, b, c, d, p, q, r):
def logic():
p.next = a | b
q.next = c & d
r.next = a ^ c
q.next[0] = c | d
return always_comb(logic)
@block
def design_v(name, a, b, c, d, p, q, r):
return setupCosimulation(**locals())
class AlwaysCombSimulationTest(TestCase):
@ -98,8 +109,8 @@ class AlwaysCombSimulationTest(TestCase):
p_v = Signal(bool(0))
q_v = Signal(intbv(0)[8:])
r_v = Signal(bool(0))
vectors = [intbv(j) for i in range(50) for j in range(16)]
random.shuffle(vectors)
vectors = [intbv(j) for __ in range(50) for j in range(16)]
shuffle(vectors)
design_inst = design(a, b, c, d, p, q, r).convert(hdl='Verilog')
design_v_inst = design_v(design.__name__, a, b, c, d, p_v, q_v, r_v)
@ -122,28 +133,26 @@ class AlwaysCombSimulationTest(TestCase):
self.assertEqual(p, p_v)
self.assertEqual(q, q_v)
self.assertEqual(r, r_v)
raise StopSimulation("always_comb simulation test")
return design_inst, design_v_inst, clkGen(), stimulus()
def test1(self):
Simulation(self.bench(design1)).run(quiet=QUIET)
def test2(self):
Simulation(self.bench(design2)).run(quiet=QUIET)
def test3(self):
Simulation(self.bench(design3)).run(quiet=QUIET)
def test4(self):
Simulation(self.bench(design4)).run(quiet=QUIET)
def test5(self):
Simulation(self.bench(design5)).run(quiet=QUIET)
if __name__ == "__main__":
unittest.main()

39
myhdl/test/conversion/toVerilog/test_beh.py
View File

@ -6,13 +6,14 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance, StopSimulation,)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def behRef(count, enable, clock, reset, n):
@ -35,30 +36,33 @@ def behRef(count, enable, clock, reset, n):
return logic
objfile = "beh_inst.o"
analyze_cmd = "iverilog -o %s beh_inst.v tb_beh_inst.v" % objfile
simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
def beh_v(name, count, enable, clock, reset):
return setupCosimulation(**locals())
class TestBeh(TestCase):
def clockGen(self, clock):
while 1:
yield delay(10)
clock.next = not clock
def stimulus(self, enable, clock, reset):
reset.next = INACTIVE_HIGH
yield clock.negedge
reset.next = ACTIVE_LOW
yield clock.negedge
reset.next = INACTIVE_HIGH
for i in range(1000):
for dummy in range(1000):
enable.next = 1
yield clock.negedge
for i in range(1000):
for dummy in range(1000):
enable.next = min(1, randrange(5))
yield clock.negedge
raise StopSimulation
@ -71,16 +75,16 @@ class TestBeh(TestCase):
yield delay(1)
# print "%d count %s count_v %s" % (now(), count, count_v)
self.assertEqual(count, count_v)
def bench(self, beh):
m = 8
n = 2 ** m
count = Signal(intbv(0)[m:])
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for __ in range(2)]
beh_inst = beh(count, enable, clock, reset, n=n).convert(hdl='Verilog')
# beh_inst = beh(count, enable, clock, reset, n=n)
@ -96,21 +100,8 @@ class TestBeh(TestCase):
def testBehRef(self):
sim = self.bench(behRef)
sim.run(quiet=1)
if __name__ == '__main__':
unittest.main()

52
myhdl/test/conversion/toVerilog/test_bin2gray.py
View File

@ -3,11 +3,12 @@ path = os.path
import unittest
from unittest import TestCase
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always_comb, instance)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
@block
def bin2gray2(B, G, width):
""" Gray encoder.
@ -16,19 +17,22 @@ def bin2gray2(B, G, width):
G -- output intbv signal, gray encoded
width -- bit width
"""
@instance
def logic():
Bext = intbv(0)[width+1:]
Bext = intbv(0)[width + 1:]
while 1:
yield B
Bext[:] = B
for i in range(width):
G.next[i] = Bext[i+1] ^ Bext[i]
G.next[i] = Bext[i + 1] ^ Bext[i]
return logic
@block
def bin2gray(B, G, width):
""" Gray encoder.
B -- input intbv signal, binary encoded
@ -39,24 +43,25 @@ def bin2gray(B, G, width):
@always_comb
def logic():
Bext = intbv(0)[width+1:]
Bext = intbv(0)[width + 1:]
Bext[:] = B
for i in range(width):
G.next[i] = Bext[i+1] ^ Bext[i]
G.next[i] = Bext[i + 1] ^ Bext[i]
return logic
objfile = "bin2gray.o"
objfile = "bin2gray.o"
analyze_cmd = "iverilog -o %s bin2gray_inst.v tb_bin2gray_inst.v" % objfile
simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
@block
def bin2gray_v(B, G):
if path.exists(objfile):
os.remove(objfile)
os.system(analyze_cmd)
return Cosimulation(simulate_cmd, **locals())
# @block
# def bin2gray_v(B, G):
# if path.exists(objfile):
# os.remove(objfile)
# os.system(analyze_cmd)
# return Cosimulation(simulate_cmd, **locals())
@block
def bin2gray_v(name, B, G):
@ -76,12 +81,12 @@ class TestBin2Gray(TestCase):
bin2gray_v_inst = bin2gray_v(bin2gray.__name__, B, G_v)
def stimulus():
for i in range(2**width):
for i in range(2 ** width):
B.next = intbv(i)
yield delay(10)
#print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
#print bin(G, width)
#print bin(G_v, width)
# print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
# print bin(G, width)
# print bin(G_v, width)
self.assertEqual(G, G_v)
return bin2gray_v_inst, stimulus(), bin2gray_inst
@ -89,13 +94,12 @@ class TestBin2Gray(TestCase):
def test1(self):
sim = self.bench(width=8, bin2gray=bin2gray)
Simulation(sim).run()
def test2(self):
sim = self.bench(width=8, bin2gray=bin2gray2)
Simulation(sim).run()
if __name__ == '__main__':
unittest.main()

94
myhdl/test/conversion/toVerilog/test_bugreports.py
View File

@ -1,5 +1,4 @@
import myhdl
from myhdl import *
from myhdl import (block, Signal, enum, intbv, always_comb, instances)
from .util import verilogCompile
@ -10,97 +9,108 @@ from .util import verilogCompile
width = 8
@block
def add(x,a,b) :
def logic() :
def add(x, a, b):
def logic():
x.next = a + b
L0 = always_comb(logic)
return L0
@block
def add3(x,a,b,c) :
x0 = Signal(intbv(0,min=-2**(width-1),max=2**(width-1)))
A0 = add(x0,a,b)
A1 = add(x,x0,c)
def add3(x, a, b, c):
x0 = Signal(intbv(0, min=-2 ** (width - 1), max=2 ** (width - 1)))
A0 = add(x0, a, b)
A1 = add(x, x0, c)
return instances()
@block
def DUT_Verilog_001(x,a,b,c,d,e) :
x0 = Signal(intbv(0,min=-2**(width-1),max=2**(width-1)))
A0 = add3(x0,a,b,c)
A1 = add3(x,x0,d,e)
@block
def DUT_Verilog_001(x, a, b, c, d, e):
x0 = Signal(intbv(0, min=-2 ** (width - 1), max=2 ** (width - 1)))
A0 = add3(x0, a, b, c)
A1 = add3(x, x0, d, e)
return instances()
def test_bugreports_001():
x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)]
x, a, b, c, d, e = [Signal(intbv(0, min=-2 ** (width - 1), max=2 ** (width - 1))) for i in range(6)]
DUT_Verilog_001(x,a,b,c,d,e).convert(hdl='Verilog')
#verilogCompile(TestModule.__name__)
#test()
DUT_Verilog_001(x, a, b, c, d, e).convert(hdl='Verilog')
# verilogCompile(TestModule.__name__)
# test()
##############################
# Bug report (Tom Dillon)
# Conflicts in reg/wire names
###############################
@block
def add(x,a,b) :
def logic() :
x.next = a + b
L0 = always_comb(logic)
return L0
# @block
# def add(x, a, b):
#
# def logic():
# x.next = a + b
#
# L0 = always_comb(logic)
# return L0
@block
def add4(x,a,b,c,d) :
xL = [Signal(intbv(0,min=-2**(width+2),max=2**(width+2))) for i in range(2)]
def add4(x, a, b, c, d):
xL = [Signal(intbv(0, min=-2 ** (width + 2), max=2 ** (width + 2))) for i in range(2)]
#xl0 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2)))
#xl1 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2)))
# xl0 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2)))
# xl1 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2)))
A0 = add(xL[0],a,b)
A1 = add(xL[1],xL[0],c)
A2 = add(x, xL[1],d)
A0 = add(xL[0], a, b)
A1 = add(xL[1], xL[0], c)
A2 = add(x, xL[1], d)
return instances()
@block
def DUT_Verilog_002(x,a,b,c,d,e):
x0 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2)))
A0 = add4(x0,a,b,c,d)
A1 = add4(x,x0,e,a,b)
@block
def DUT_Verilog_002(x, a, b, c, d, e):
x0 = Signal(intbv(0, min=-2 ** (width + 2), max=2 ** (width + 2)))
A0 = add4(x0, a, b, c, d)
A1 = add4(x, x0, e, a, b)
return instances()
def test_bugreports_002():
width = 8
x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)]
x, a, b, c, d, e = [Signal(intbv(0, min=-2 ** (width - 1), max=2 ** (width - 1))) for __ in range(6)]
DUT_Verilog_002(x,a,b,c,d,e).convert(hdl='Verilog')
DUT_Verilog_002(x, a, b, c, d, e).convert(hdl='Verilog')
verilogCompile(DUT_Verilog_002.__name__)
#test()
# test()
###################################
# Bug report (George Pantazopoulos)
# case variable name in embedded FSM
####################################
from .test_fsm import FramerCtrl
@block
def mid(SOF, clk, reset_n):
t_State = enum('SEARCH', 'CONFIRM', 'SYNC')
syncFlag = Signal(bool(0))
state = Signal(t_State.SEARCH)
fsm_1 = FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State)
return fsm_1
@ -116,9 +126,9 @@ def test_bugreports_003():
clk = Signal(bool(0))
reset_n = Signal(bool(1))
SOF = Signal(bool(0))
DUT_Verilog_003(SOF, clk, reset_n).convert()
verilogCompile(DUT_Verilog_003.__name__)
#test()
# test()

52
myhdl/test/conversion/toVerilog/test_custom.py
View File

@ -6,17 +6,17 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from .util import setupCosimulation
from myhdl import (block, Signal, intbv, delay, always, always_comb ,
instance, StopSimulation, toVerilog)
from myhdl._Simulation import Simulation
from myhdl import ConversionError
from myhdl.conversion._misc import _error
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def incRef(count, enable, clock, reset, n):
""" Incrementer with enable.
@ -27,6 +27,7 @@ def incRef(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@instance
def logic():
while 1:
@ -36,12 +37,14 @@ def incRef(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@block
def incGen(count, enable, clock, reset, n):
""" Generator with verilog_code is not permitted """
@instance
def logic():
incGen.verilog_code = "Template string"
@ -52,6 +55,7 @@ def incGen(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@ -65,6 +69,7 @@ def inc(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@always(clock.posedge, reset.negedge)
def incProcess():
# make it fail in conversion
@ -126,7 +131,6 @@ end
return incProcess
@block
def inc_comb(nextCount, count, n):
@ -138,13 +142,14 @@ def inc_comb(nextCount, count, n):
nextCount.driven = "wire"
inc_comb.verilog_code =\
inc_comb.verilog_code = \
"""
assign $nextCount = ($count + 1) % $n;
"""
return logic
@block
def inc_seq(count, nextCount, enable, clock, reset):
@ -175,6 +180,7 @@ end
"""
return logic
@block
def inc2(count, enable, clock, reset, n):
@ -191,7 +197,9 @@ def inc3(count, enable, clock, reset, n):
inc2_inst = inc2(count, enable, clock, reset, n)
return inc2_inst
class ClassIncrementer(object):
@block
def inc(self, count, enable, clock, reset, n):
""" Incrementer with enable.
@ -202,6 +210,7 @@ class ClassIncrementer(object):
reset -- asynchronous reset input
n -- counter max value
"""
@always(clock.posedge, reset.negedge)
def incProcess():
# make it fail in conversion
@ -234,6 +243,7 @@ class ClassIncrementer(object):
def inc_v(name, count, enable, clock, reset):
return setupCosimulation(**locals())
class TestInc(TestCase):
def clockGen(self, clock):
@ -247,10 +257,10 @@ class TestInc(TestCase):
reset.next = ACTIVE_LOW
yield clock.negedge
reset.next = INACTIVE_HIGH
for i in range(1000):
for dummy in range(1000):
enable.next = 1
yield clock.negedge
for i in range(1000):
for dummy in range(1000):
enable.next = min(1, randrange(5))
yield clock.negedge
raise StopSimulation
@ -277,7 +287,7 @@ class TestInc(TestCase):
count = Signal(intbv(0)[m:])
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for __ in range(2)]
inc_inst_ref = incRef(count, enable, clock, reset, n=n)
inc_inst = toVerilog(incVer(count, enable, clock, reset, n=n))
@ -316,7 +326,7 @@ class TestInc(TestCase):
n = 2 ** m
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for __ in range(2)]
try:
inc_inst = toVerilog(incGen(count_v, enable, clock, reset, n=n))
except ConversionError as e:
@ -329,10 +339,10 @@ class TestInc(TestCase):
n = 2 ** m
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for __ in range(2)]
try:
inc_inst = toVerilog(incErr(count_v, enable, clock, reset, n=n))
except ConversionError as e:
except ConversionError:
pass
else:
self.fail()
@ -343,22 +353,6 @@ class TestInc(TestCase):
sim.run(quiet=1)
if __name__ == '__main__':
unittest.main()

79
myhdl/test/conversion/toVerilog/test_dec.py
View File

@ -6,13 +6,15 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always,
instance, StopSimulation)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def decRef(count, enable, clock, reset, n):
""" Decrementer with enable.
@ -23,6 +25,7 @@ def decRef(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@instance
def logic():
while 1:
@ -32,12 +35,14 @@ def decRef(count, enable, clock, reset, n):
else:
if enable:
if count == -n:
count.next = n-1
count.next = n - 1
else:
count.next = count - 1
return logic
@block
@block
def dec(count, enable, clock, reset, n):
""" Decrementer with enable.
@ -47,6 +52,7 @@ def dec(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@instance
def decProcess():
while 1:
@ -56,18 +62,20 @@ def dec(count, enable, clock, reset, n):
else:
if enable:
if count == -n:
count.next = n-1
count.next = n - 1
else:
count.next = count - 1
return decProcess
@block
def decFunc(count, enable, clock, reset, n):
def decFuncFunc(cnt):
count_next = intbv(0, min=-n, max=n)
if count == -n:
count_next[:] = n-1
count_next[:] = n - 1
else:
count_next[:] = cnt - 1
return count_next
@ -82,13 +90,14 @@ def decFunc(count, enable, clock, reset, n):
return decFuncGen
@block
def decTask(count, enable, clock, reset, n):
def decTaskFunc(cnt, enable, reset, n):
if enable:
if cnt == -n:
cnt.next = n-1
cnt.next = n - 1
else:
cnt.next = cnt - 1
@ -107,13 +116,14 @@ def decTask(count, enable, clock, reset, n):
return decTaskGen
@block
def decTaskFreeVar(count, enable, clock, reset, n):
def decTaskFunc():
if enable:
if count == -n:
count.next = n-1
count.next = n - 1
else:
count.next = count - 1
@ -122,7 +132,7 @@ def decTaskFreeVar(count, enable, clock, reset, n):
while 1:
yield clock.posedge, reset.negedge
if reset == ACTIVE_LOW:
count.next = 0
count.next = 0
else:
# print count
decTaskFunc()
@ -130,27 +140,27 @@ def decTaskFreeVar(count, enable, clock, reset, n):
return decTaskGen
def dec_v(name, count, enable, clock, reset):
return setupCosimulation(**locals())
class TestDec(TestCase):
def clockGen(self, clock):
while 1:
yield delay(10)
clock.next = not clock
def stimulus(self, enable, clock, reset):
reset.next = INACTIVE_HIGH
yield clock.negedge
reset.next = ACTIVE_LOW
yield clock.negedge
reset.next = INACTIVE_HIGH
for i in range(1000):
for dummy in range(1000):
enable.next = 1
yield clock.negedge
for i in range(1000):
for dummy in range(1000):
enable.next = min(1, randrange(5))
yield clock.negedge
raise StopSimulation
@ -164,23 +174,23 @@ class TestDec(TestCase):
yield clock.posedge
if enable:
if expect == -n:
expect = n-1
expect = n - 1
else:
expect -= 1
yield delay(1)
# print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
self.assertEqual(count, expect)
self.assertEqual(count, count_v)
def bench(self, dec):
m = 8
n = 2 ** (m-1)
n = 2 ** (m - 1)
count = Signal(intbv(0, min=-n, max=n))
count_v = Signal(intbv(0, min=-n, max=n))
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for __ in range(2)]
dec_inst_ref = decRef(count, enable, clock, reset, n=n)
dec_inst = dec(count, enable, clock, reset, n=n).convert(hdl='Verilog')
@ -196,38 +206,25 @@ class TestDec(TestCase):
def testDecRef(self):
sim = self.bench(decRef)
sim.run(quiet=1)
def testDec(self):
sim = self.bench(dec)
sim.run(quiet=1)
def testDecFunc(self):
sim = self.bench(decFunc)
sim.run(quiet=1)
## signed inout in task doesn't work yet in Icarus
## def testDecTask(self):
## sim = self.bench(decTask)
## sim.run(quiet=1)
# # signed inout in task doesn't work yet in Icarus
# # def testDecTask(self):
# # sim = self.bench(decTask)
# # sim.run(quiet=1)
def testDecTaskFreeVar(self):
sim = self.bench(decTaskFreeVar)
sim.run(quiet=0)
if __name__ == '__main__':
unittest.main()

39
myhdl/test/conversion/toVerilog/test_edge.py
View File

@ -6,13 +6,15 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, delay, always,
instance, StopSimulation)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def edge1(flag, sig, clock):
@ -27,6 +29,7 @@ def edge1(flag, sig, clock):
return detect
@block
def edge2(flag, sig, clock):
@ -39,6 +42,7 @@ def edge2(flag, sig, clock):
return detect
@block
def edge3(flag, sig, clock):
@ -66,13 +70,14 @@ def edge4(flag, sig, clock):
return detect
@block
def edge_v(name, flag, sig, clock):
return setupCosimulation(**locals())
class TestEdge(TestCase):
def bench(self, edge):
clock = Signal(bool(0))
@ -89,7 +94,7 @@ class TestEdge(TestCase):
@instance
def stimulus():
yield clock.negedge
for i in range(100):
for dummy in range(100):
sig.next = randrange(2)
yield clock.negedge
raise StopSimulation
@ -108,40 +113,24 @@ class TestEdge(TestCase):
edge_inst_v = edge_v(edge.__name__, flag, sig, clock)
return clockgen, stimulus, delayline, check, edge_inst_v
def testEdge1(self):
sim = Simulation(self.bench(edge1))
sim.run(quiet=1)
def testEdge2(self):
sim = Simulation(self.bench(edge2))
sim.run(quiet=1)
def testEdge3(self):
sim = Simulation(self.bench(edge3))
sim.run(quiet=1)
def testEdge4(self):
sim = Simulation(self.bench(edge4))
sim.run(quiet=1)
if __name__ == '__main__':
unittest.main()

218
myhdl/test/conversion/toVerilog/test_errors.py
View File

@ -6,58 +6,71 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, downrange,
instance, StopSimulation)
from myhdl._Simulation import Simulation
from myhdl import ConversionError
from myhdl.conversion._misc import _error
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def freeVarTypeError(count, enable, clock, reset, n):
cnt = intbv(0)[8:]
def incTaskFunc():
if enable:
cnt[:] = (cnt + 1) % n
@instance
def incTaskGen():
while 1:
yield clock.posedge, reset.negedge
if reset == ACTIVE_LOW:
cnt[:]= 0
cnt[:] = 0
else:
incTaskFunc()
return incTaskGen
@block
def multipleDrivenSignal(count, enable, clock, reset, n):
@instance
def incTaskGen():
while 1:
yield clock.posedge, reset.negedge
if reset == ACTIVE_LOW:
count.next = 0
count.next = 0
else:
if enable:
count.next = (count + 1) % n
return incTaskGen, incTaskGen
@block
def shadowingSignal(count, enable, clock, reset, n):
count = Signal(intbv(0)[8:])
@instance
def incTaskGen():
while 1:
yield clock.posedge, reset.negedge
if reset == ACTIVE_LOW:
count.next = 0
count.next = 0
else:
if enable:
count.next = (count + 1) % n
return incTaskGen
@block
def internalSignal(count, enable, clock, reset, n):
@instance
def logic():
a = Signal(bool())
@ -68,25 +81,30 @@ def internalSignal(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@block
def undefinedBitWidthSignal(count, enable, clock, reset, n):
count = Signal(intbv(0))
@instance
def incTaskGen():
while 1:
yield clock.posedge, reset.negedge
if reset == ACTIVE_LOW:
count.next = 0
count.next = 0
else:
if enable:
count.next = (count + 1) % n
return incTaskGen
@block
def yieldObject1(count, enable, clock, reset, n):
@instance
def logic():
while 1:
@ -96,15 +114,21 @@ def yieldObject1(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
def g1(clock):
yield clock.posedge
def g2(reset):
yield reset.negedge
@block
def yieldObject2(count, enable, clock, reset, n):
@instance
def logic():
while 1:
@ -114,28 +138,34 @@ def yieldObject2(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
def f1(n):
if n == 0:
return 0
else:
return f1(n-1)
return f1(n - 1)
def f2(n):
if n == 0:
return 1
else:
return f3(n-1)
return f3(n - 1)
def f3(n):
if n == 0:
return 1
else:
return f2(n-1)
return f2(n - 1)
@block
def recursion1(count, enable, clock, reset, n):
@instance
def logic():
while 1:
@ -145,10 +175,13 @@ def recursion1(count, enable, clock, reset, n):
else:
if enable:
count.next = f1(n)
return logic
@block
def recursion2(count, enable, clock, reset, n):
@instance
def logic():
while 1:
@ -158,14 +191,18 @@ def recursion2(count, enable, clock, reset, n):
else:
if enable:
count.next = f2(n)
return logic
def h1(n):
pass
# return None
@block
def functionNoReturnVal(count, enable, clock, reset, n):
@instance
def logic():
while 1:
@ -175,14 +212,18 @@ def functionNoReturnVal(count, enable, clock, reset, n):
else:
if enable:
count.next = h1(n)
return logic
def h2(cnt):
cnt[:] = cnt + 1
return 1
@block
def taskReturnVal(count, enable, clock, reset, n):
@instance
def logic():
cnt = intbv(0)[8:]
@ -194,101 +235,124 @@ def taskReturnVal(count, enable, clock, reset, n):
if enable:
h2(cnt)
count.next = count + 1
return logic
@block
def listComp1(count, enable, clock, reset, n):
@instance
def logic():
mem = [intbv(0)[8:] for i in range(4) for j in range(5)]
mem = [intbv(0)[8:] for dummy in range(4) for dummy in range(5)]
while 1:
yield clock.posedge, reset.negedge
count.next = count + 1
return logic
@block
def listComp2(count, enable, clock, reset, n):
@instance
def logic():
mem = [intbv(0)[8:] for i in downrange(4)]
mem = [intbv(0)[8:] for dummy in downrange(4)]
while 1:
yield clock.posedge, reset.negedge
count.next = count + 1
return logic
@block
def listComp3(count, enable, clock, reset, n):
@instance
def logic():
mem = [intbv(0)[8:] for i in range(1, 4)]
mem = [intbv(0)[8:] for dummy in range(1, 4)]
while 1:
yield clock.posedge, reset.negedge
count.next = count + 1
return logic
@block
def listComp4(count, enable, clock, reset, n):
@instance
def logic():
mem = [intbv(0) for i in range(4)]
mem = [intbv(0) for dummy in range(4)]
while 1:
yield clock.posedge, reset.negedge
count.next = count + 1
return logic
@block
def listComp5(count, enable, clock, reset, n):
@instance
def logic():
mem = [i for i in range(4)]
while 1:
yield clock.posedge, reset.negedge
count.next = count + 1
return logic
@block
def undefinedBitWidthMem(count, enable, clock, reset, n):
mem = [Signal(intbv(0)[8:]) for i in range(8)]
mem[7] = Signal(intbv(0))
@instance
def f():
while 1:
yield clock.posedge, reset.negedge
count.next = mem[0] + 1
return f
@block
def inconsistentTypeMem(count, enable, clock, reset, n):
mem = [Signal(intbv(0)[8:]) for i in range(8)]
mem = [Signal(intbv(0)[8:]) for __ in range(8)]
mem[3] = Signal(bool())
@instance
def f():
while 1:
yield clock.posedge, reset.negedge
count.next = mem[0] + 1
return f
@block
def inconsistentBitWidthMem(count, enable, clock, reset, n):
mem = [Signal(intbv(0)[8:]) for i in range(8)]
mem = [Signal(intbv(0)[8:]) for __ in range(8)]
mem[4] = Signal(intbv(0)[7:])
@instance
def f():
while 1:
yield clock.posedge, reset.negedge
count.next = mem[0] + 1
return f
## def listElementNotUnique(count, enable, clock, reset, n):
## mem = [Signal(intbv(0)[8:]) for i in range(8)]
## mem2 = mem[4:]
## def f():
## while 1:
## yield clock.posedge, reset.negedge
## count.next = mem[0] + mem2[1]
## return f()
# # def listElementNotUnique(count, enable, clock, reset, n):
# # mem = [Signal(intbv(0)[8:]) for i in range(8)]
# # mem2 = mem[4:]
# # def f():
# # while 1:
# # yield clock.posedge, reset.negedge
# # count.next = mem[0] + mem2[1]
# # return f()
class TestErr(TestCase):
@ -297,17 +361,17 @@ class TestErr(TestCase):
while 1:
yield delay(10)
clock.next = not clock
def stimulus(self, enable, clock, reset):
reset.next = INACTIVE_HIGH
yield clock.negedge
reset.next = ACTIVE_LOW
yield clock.negedge
reset.next = INACTIVE_HIGH
for i in range(1000):
for dummy in range(1000):
enable.next = 1
yield clock.negedge
for i in range(1000):
for dummy in range(1000):
enable.next = min(1, randrange(5))
yield clock.negedge
raise StopSimulation
@ -325,16 +389,16 @@ class TestErr(TestCase):
# print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
self.assertEqual(count, expect)
self.assertEqual(count, count_v)
def bench(self, err):
m = 8
n = 2 ** m
count = Signal(intbv(0)[m:])
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for __ in range(2)]
err_inst = err(count, enable, clock, reset, n=n).convert(hdl='Verilog')
clk_1 = self.clockGen(clock)
@ -344,7 +408,6 @@ class TestErr(TestCase):
sim = Simulation(err_inst, clk_1, st_1, ch_1)
return sim
def testInternalSignal(self):
try:
self.bench(internalSignal)
@ -352,7 +415,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.TypeInfer)
else:
self.fail()
def testMultipleDrivenSignal(self):
try:
self.bench(multipleDrivenSignal)
@ -360,7 +423,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.SigMultipleDriven)
else:
self.fail()
def testShadowingSignal(self):
try:
self.bench(shadowingSignal)
@ -376,7 +439,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.UndefinedBitWidth)
else:
self.fail()
def testFreeVarTypeError(self):
try:
self.bench(freeVarTypeError)
@ -384,15 +447,15 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.FreeVarTypeError)
else:
self.fail()
## def testNegIntbv(self):
## try:
## self.bench(negIntbv)
## except ConversionError, e:
## self.assertEqual(e.kind, _error.IntbvSign)
## else:
## self.fail()
# # def testNegIntbv(self):
# # try:
# # self.bench(negIntbv)
# # except ConversionError, e:
# # self.assertEqual(e.kind, _error.IntbvSign)
# # else:
# # self.fail()
def testYield1(self):
try:
self.bench(yieldObject1)
@ -400,7 +463,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.UnsupportedYield)
else:
self.fail()
def testYield2(self):
try:
self.bench(yieldObject2)
@ -408,7 +471,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.NotSupported)
else:
self.fail()
def testRecursion1(self):
try:
self.bench(recursion1)
@ -416,7 +479,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.NotSupported)
else:
self.fail()
def testRecursion2(self):
try:
self.bench(recursion2)
@ -424,7 +487,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.NotSupported)
else:
self.fail()
def testFunctionNoReturnVal(self):
try:
self.bench(functionNoReturnVal)
@ -432,7 +495,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.NotSupported)
else:
self.fail()
def testTaskReturnVal(self):
try:
self.bench(taskReturnVal)
@ -448,7 +511,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.NotSupported)
else:
self.fail()
def testListComp2(self):
try:
self.bench(listComp2)
@ -456,7 +519,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.UnsupportedListComp)
else:
self.fail()
def testListComp3(self):
try:
self.bench(listComp3)
@ -464,7 +527,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.UnsupportedListComp)
else:
self.fail()
def testListComp4(self):
try:
self.bench(listComp4)
@ -472,7 +535,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.UnsupportedListComp)
else:
self.fail()
def testListComp5(self):
try:
self.bench(listComp5)
@ -480,7 +543,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.UnsupportedListComp)
else:
self.fail()
def testUndefinedBitWidthMem(self):
try:
self.bench(undefinedBitWidthMem)
@ -488,7 +551,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.UndefinedBitWidth)
else:
self.fail()
def testInconsistentTypeMem(self):
try:
self.bench(inconsistentTypeMem)
@ -496,7 +559,7 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.InconsistentType)
else:
self.fail()
def testInconsistentBitWidthMem(self):
try:
self.bench(inconsistentBitWidthMem)
@ -504,29 +567,16 @@ class TestErr(TestCase):
self.assertEqual(e.kind, _error.InconsistentBitWidth)
else:
self.fail()
## def testListElementNotUnique(self):
## try:
## self.bench(listElementNotUnique)
## except ConversionError, e:
## self.assertEqual(e.kind, _error.ListElementNotUnique)
## else:
## self.fail()
# # def testListElementNotUnique(self):
# # try:
# # self.bench(listElementNotUnique)
# # except ConversionError, e:
# # self.assertEqual(e.kind, _error.ListElementNotUnique)
# # else:
# # self.fail()
if __name__ == '__main__':
unittest.main()

4
myhdl/test/conversion/toVerilog/test_fsm.py
View File

@ -193,13 +193,13 @@ class FramerCtrlTest(TestCase):
@instance
def stimulus():
for __ in range(3):
for dummy in range(3):
yield clk.posedge
for n in (12, 8, 8, 4, 11, 8, 8, 7, 6, 8, 8):
syncFlag.next = 1
yield clk.posedge
syncFlag.next = 0
for __ in range(n - 1):
for dummy in range(n - 1):
yield clk.posedge
raise StopSimulation

41
myhdl/test/conversion/toVerilog/test_hec.py
View File

@ -3,13 +3,14 @@ path = os.path
import unittest
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay,
instance, concat, downrange)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
COSET = 0x55
def calculateHecRef(header):
""" Return hec for an ATM header.
@ -25,6 +26,7 @@ def calculateHecRef(header):
)
return hec ^ COSET
def calculateHecFunc(header):
""" Return hec for an ATM header.
@ -42,6 +44,7 @@ def calculateHecFunc(header):
h ^= COSET
return h
def calculateHecTask(hec, header):
""" Calculate hec for an ATM header.
@ -59,12 +62,14 @@ def calculateHecTask(hec, header):
h ^= COSET
hec[:] = h
@block
def HecCalculatorPlain(hec, header):
""" Hec calculation module.
Plain version.
"""
@instance
def logic():
h = intbv(0)[8:]
@ -79,28 +84,33 @@ def HecCalculatorPlain(hec, header):
bit ^ h[7]
)
hec.next = h ^ COSET
return logic
@block
def HecCalculatorFunc(hec, header=1):
""" Hec calculation module.
Version with function call.
"""
@instance
def logic():
h = intbv(0)[8:]
while 1:
yield header
hec.next = calculateHecFunc(header=header)
return logic
@block
def HecCalculatorTask(hec, header):
""" Hec calculation module.
Version with task call.
"""
@instance
def logic():
h = intbv(0)[8:]
@ -108,14 +118,17 @@ def HecCalculatorTask(hec, header):
yield header
calculateHecTask(h, header)
hec.next = h
return logic
@block
def HecCalculatorTask2(hec, header):
""" Hec calculation module.
Version with task call.
"""
@instance
def logic():
h = intbv(0)[8:]
@ -123,27 +136,27 @@ def HecCalculatorTask2(hec, header):
yield header
calculateHecTask(header=header, hec=h)
hec.next = h
return logic
@block
def HecCalculator_v(name, hec, header):
return setupCosimulation(**locals())
headers = [ 0x00000000,
0x01234567,
0xbac6f4ca
]
headers.extend([randrange(2**32-1) for i in range(10)])
headers.extend([randrange(2 ** 32 - 1) for i in range(10)])
class TestHec(unittest.TestCase):
def bench(self, HecCalculator):
hec = Signal(intbv(0)[8:])
hec_v = Signal(intbv(0)[8:])
header = Signal(intbv(-1)[32:])
@ -151,7 +164,7 @@ class TestHec(unittest.TestCase):
heccalc_inst = HecCalculator(hec, header).convert(hdl='Verilog')
# heccalc_inst = HecCalculator(hec, header)
heccalc_v_inst = HecCalculator_v(HecCalculator.__name__, hec_v, header)
def stimulus():
for h in headers:
header.next = h
@ -174,11 +187,11 @@ class TestHec(unittest.TestCase):
def testTask(self):
sim = self.bench(HecCalculatorTask)
Simulation(sim).run()
def testTask2(self):
sim = self.bench(HecCalculatorTask2)
Simulation(sim).run()
if __name__ == '__main__':
unittest.main()

70
myhdl/test/conversion/toVerilog/test_inc.py
View File

@ -6,13 +6,14 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always,
instance, StopSimulation)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def incRef(count, enable, clock, reset, n):
""" Incrementer with enable.
@ -23,6 +24,7 @@ def incRef(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@instance
def logic():
while 1:
@ -32,11 +34,13 @@ def incRef(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@block
def inc(count, enable, clock, reset, n):
""" Incrementer with enable.
count -- output
@ -46,7 +50,7 @@ def inc(count, enable, clock, reset, n):
n -- counter max value
"""
@always(clock.posedge, reset.negedge)
def incProcess():
if reset == ACTIVE_LOW:
@ -54,28 +58,30 @@ def inc(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return incProcess
@block
def inc2(count, enable, clock, reset, n):
@always(clock.posedge, reset.negedge)
def incProcess():
if reset == ACTIVE_LOW:
count.next = 0
else:
if enable:
if count == n-1:
if count == n - 1:
count.next = 0
else:
count.next = count + 1
return incProcess
@block
def incTask(count, enable, clock, reset, n):
def incTaskFunc(cnt, enable, reset, n):
if enable:
cnt[:] = (cnt + 1) % n
@ -95,9 +101,10 @@ def incTask(count, enable, clock, reset, n):
return incTaskGen
@block
def incTaskFreeVar(count, enable, clock, reset, n):
def incTaskFunc():
if enable:
count.next = (count + 1) % n
@ -105,35 +112,36 @@ def incTaskFreeVar(count, enable, clock, reset, n):
@always(clock.posedge, reset.negedge)
def incTaskGen():
if reset == ACTIVE_LOW:
count.next = 0
count.next = 0
else:
# print count
incTaskFunc()
return incTaskGen
@block
def inc_v(name, count, enable, clock, reset):
return setupCosimulation(**locals())
class TestInc(TestCase):
def clockGen(self, clock):
while 1:
yield delay(10)
clock.next = not clock
def stimulus(self, enable, clock, reset):
reset.next = INACTIVE_HIGH
yield clock.negedge
reset.next = ACTIVE_LOW
yield clock.negedge
reset.next = INACTIVE_HIGH
for i in range(1000):
for dummy in range(1000):
enable.next = 1
yield clock.negedge
for i in range(1000):
for dummy in range(1000):
enable.next = min(1, randrange(5))
yield clock.negedge
raise StopSimulation
@ -151,16 +159,16 @@ class TestInc(TestCase):
# print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
self.assertEqual(count, expect)
self.assertEqual(count, count_v)
def bench(self, inc):
m = 8
n = 2 ** m
count = Signal(intbv(0)[m:])
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for __ in range(2)]
inc_inst_ref = incRef(count, enable, clock, reset, n=n)
inc_inst = inc(count, enable, clock, reset, n=n).convert(hdl='Verilog')
@ -177,36 +185,22 @@ class TestInc(TestCase):
""" Check increment operation """
sim = self.bench(incRef)
sim.run(quiet=1)
def testInc(self):
""" Check increment operation """
sim = self.bench(inc)
sim.run(quiet=1)
def testInc2(self):
""" Check increment operation """
sim = self.bench(inc2)
sim.run(quiet=1)
def testIncTask(self):
sim = self.bench(incTask)
sim.run(quiet=1)
def testIncTaskFreeVar(self):
sim = self.bench(incTaskFreeVar)
sim.run(quiet=1)

45
myhdl/test/conversion/toVerilog/test_inc_initial.py
View File

@ -6,13 +6,15 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay,
instance, StopSimulation, negedge)
from myhdl._Simulation import Simulation, Cosimulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def inc_initial(count, enable, clock, reset, n):
""" Incrementer with enable.
@ -23,9 +25,10 @@ def inc_initial(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@instance
def logic():
for i in range(100):
for dummy in range(100):
yield clock.posedge, reset.negedge
if reset == ACTIVE_LOW:
count.next = 0
@ -33,15 +36,17 @@ def inc_initial(count, enable, clock, reset, n):
if enable:
count.next = (count + 1) % n
raise StopSimulation
return logic
objfile = "inc_initial_1.o"
analyze_cmd = "iverilog -o %s inc_initial_1.v tb_inc_initial_1.v" % objfile
vpifile = "../../../cosimulation/icarus/myhdl.vpi"
#vpifile = "cosimulation/icarus/myhdl.vpi"
# vpifile = "cosimulation/icarus/myhdl.vpi"
simulate_cmd = "vvp -m %s %s" % (vpifile, objfile)
def top(name, count, enable, clock, reset, n, arch="myhdl"):
if arch == "verilog":
return setupCosimulation(**locals())
@ -53,18 +58,19 @@ def top(name, count, enable, clock, reset, n, arch="myhdl"):
inc_initial_inst = inc_initial(count, enable, clock, reset, n)
return inc_initial_inst
class TestInc_initial(TestCase):
def clockGen(self, clock):
while 1:
yield delay(10)
clock.next = not clock
def stimulus(self, enable, clock, reset):
reset.next = ACTIVE_LOW
yield negedge(clock)
reset.next = INACTIVE_HIGH
for i in range(1000):
for dummy in range(1000):
enable.next = min(1, randrange(5))
yield negedge(clock)
raise StopSimulation
@ -81,15 +87,15 @@ class TestInc_initial(TestCase):
yield delay(1)
self.assertEqual(count, expect)
self.assertEqual(count, count_v)
def bench(self):
m = 8
n = 2 ** m
count = Signal(intbv(0)[m:])
count_v = Signal(intbv(0)[m:])
enable, clock, reset = [Signal(bool()) for i in range(3)]
enable, clock, reset = [Signal(bool()) for __ in range(3)]
inc_initial_1 = top(top.__name__, count, enable, clock, reset, n=n).convert(hdl='Verilog')
inc_initial_v = top(top.__name__, count_v, enable, clock, reset, n=n).convert(hdl='Verilog')
@ -104,23 +110,8 @@ class TestInc_initial(TestCase):
""" Check increment operation """
sim = self.bench()
sim.run(quiet=1)
if __name__ == '__main__':
unittest.main()

113
myhdl/test/conversion/toVerilog/test_infer.py
View File

@ -1,10 +1,10 @@
import os
path = os.path
import unittest
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, enum, intbv, delay, instance,
StopSimulation, toVerilog)
from myhdl._Simulation import Simulation
from myhdl import ConversionError
from myhdl.conversion._misc import _error
@ -12,18 +12,23 @@ from .util import setupCosimulation
b = c = 2
@block
def UnboundError1(a, out):
@instance
def logic():
while 1:
yield a
out.next = a + b
b = 1
return logic
@block
def UnboundError2(a, out):
@instance
def logic():
while 1:
@ -32,20 +37,26 @@ def UnboundError2(a, out):
c = 1
else:
out.next = c
return logic
@block
def UnboundError3(a, out):
@instance
def logic():
while 1:
yield a
out.next = a + d
out.next = a + d # this is the error we want to test
d = 1
return logic
@block
def UnboundError4(a, out):
@instance
def logic():
while 1:
@ -54,10 +65,13 @@ def UnboundError4(a, out):
e = 1
else:
out.next = e
return logic
@block
def InferError1(a, out):
@instance
def logic():
yield a
@ -65,10 +79,13 @@ def InferError1(a, out):
b = intbv(0)[5:]
b[:] = 4
out.next = b
return logic
@block
def InferError2(a, out):
@instance
def logic():
yield a
@ -77,29 +94,38 @@ def InferError2(a, out):
c = intbv(0)[4:]
c[:] = 4
out.next = c
return logic
enumType = enum("a", "b", "c")
@block
def InferError3(a, out):
@instance
def logic():
yield a
d = enumType.a
d = 4
out.next = b
return logic
@block
def InferError4(a, out):
@instance
def logic():
h = intbv(0)
yield a
out.next = h
return logic
def InferError5Func(a):
h = intbv(0)[5:]
if a:
@ -107,46 +133,56 @@ def InferError5Func(a):
else:
return 1
@block
def InferError5(a, out):
@instance
def logic():
yield a
out.next = InferError5Func(a)
return logic
def InferError6Func(a):
if a:
return intbv(0)
else:
return intbv(1)
@block
def InferError6(a, out):
@instance
def logic():
yield a
out.next = InferError6Func(a)
return logic
def InferError7Func(a):
if a:
return intbv(0)[5:]
else:
return intbv(0xff)[7:2]
@block
def InferError7(a, out):
@instance
def logic():
yield a
out.next = InferError7Func(a)
return logic
class TestErrors(unittest.TestCase):
def check(self, *args):
try:
i = toVerilog(*args)
@ -176,43 +212,43 @@ class TestErrors(unittest.TestCase):
out = Signal(intbv(0)[16:])
infertest_inst = Infertest(a, out).convert(hdl='Verilog')
def testUnboundError1(self):
sim = self.check(UnboundError1, _error.UnboundLocal)
def testUnboundError2(self):
sim = self.check(UnboundError2, _error.UnboundLocal)
def testUnboundError3(self):
sim = self.check(UnboundError3, _error.UnboundLocal)
def testUnboundError4(self):
sim = self.check(UnboundError4, _error.UnboundLocal)
def testInferError1(self):
sim = self.check(InferError1, _error.TypeMismatch)
def testInferError2(self):
sim = self.check(InferError2, _error.NrBitsMismatch)
def testInferError3(self):
sim = self.check(InferError3, _error.TypeMismatch)
def testInferError4(self):
sim = self.check(InferError4, _error.IntbvBitWidth)
def testInferError5(self):
sim = self.check(InferError5, _error.ReturnTypeMismatch)
def testInferError6(self):
sim = self.check(InferError6, _error.ReturnIntbvBitWidth)
def testInferError7(self):
sim = self.nocheck(InferError7, _error.ReturnIntbvBitWidth)
@block
def Infer1(a, out):
@instance
def logic():
while 1:
@ -224,10 +260,13 @@ def Infer1(a, out):
c = not a
c = True
out.next = c
return logic
@block
@block
def Infer2(a, out):
@instance
def logic():
while 1:
@ -239,23 +278,29 @@ def Infer2(a, out):
c = True
c = 5
out.next = c
return logic
def Infer3Func(a):
if True:
return a > 0
else:
return 5
@block
def Infer3(a, out):
@instance
def logic():
while 1:
yield a
out.next = Infer3Func(a)
return logic
def Infer4Func(a):
while 1:
if True:
@ -263,17 +308,22 @@ def Infer4Func(a):
else:
return a < 3
@block
def Infer4(a, out):
@instance
def logic():
while 1:
yield a
out.next = Infer4Func(a)
return logic
@block
def Infer5(a, out):
@instance
def logic():
while 1:
@ -285,8 +335,8 @@ def Infer5(a, out):
c = a << 2
c = a >> 2
c = a % 16
c = + a
c = -( - a)
c = +a
c = -(-a)
c = ~(-3)
c = not a
c = 5 & 4
@ -294,17 +344,18 @@ def Infer5(a, out):
c = 6 ^ 3
c = bool(a) and 1
out.next = c
return logic
def Infertest_v(name, a, out):
return setupCosimulation(**locals())
class TestInfer(unittest.TestCase):
def bench(self, Infertest):
a = Signal(intbv()[16:])
out_v = Signal(intbv(0)[16:])
out = Signal(intbv(0)[16:])
@ -312,7 +363,7 @@ class TestInfer(unittest.TestCase):
infertest_inst = Infertest(a, out).convert(hdl='Verilog')
# infertest_inst = Infertest(hec, header)
infertest_v_inst = Infertest_v(Infertest.__name__, a, out_v)
def stimulus():
a.next = 1
yield delay(10)
@ -325,11 +376,11 @@ class TestInfer(unittest.TestCase):
def testInfer1(self):
sim = self.bench(Infer1)
Simulation(sim).run()
def testInfer2(self):
sim = self.bench(Infer2)
Simulation(sim).run()
def testInfer3(self):
sim = self.bench(Infer3)
Simulation(sim).run()
@ -337,11 +388,11 @@ class TestInfer(unittest.TestCase):
def testInfer4(self):
sim = self.bench(Infer4)
Simulation(sim).run()
def testInfer5(self):
sim = self.bench(Infer5)
Simulation(sim).run()
if __name__ == '__main__':
unittest.main()

136
myhdl/test/conversion/toVerilog/test_loops.py
View File

@ -3,14 +3,16 @@ path = os.path
import unittest
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay,
instance, downrange)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
@block
def ForLoop1(a, out):
@instance
def logic():
while 1:
@ -20,10 +22,13 @@ def ForLoop1(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop2(a, out):
@instance
def logic():
while 1:
@ -33,10 +38,13 @@ def ForLoop2(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop3(a, out):
@instance
def logic():
while 1:
@ -46,10 +54,13 @@ def ForLoop3(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop4(a, out):
@instance
def logic():
while 1:
@ -59,10 +70,13 @@ def ForLoop4(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop5(a, out):
@instance
def logic():
while 1:
@ -72,10 +86,13 @@ def ForLoop5(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForLoop6(a, out):
@instance
def logic():
while 1:
@ -85,10 +102,13 @@ def ForLoop6(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
@block
def ForContinueLoop(a, out):
@instance
def logic():
while 1:
@ -99,10 +119,13 @@ def ForContinueLoop(a, out):
continue
var += 1
out.next = var
return logic
@block
def ForBreakLoop(a, out):
@instance
def logic():
while 1:
@ -112,10 +135,13 @@ def ForBreakLoop(a, out):
if a[i] == 1:
out.next = i
break
return logic
@block
def ForBreakContinueLoop(a, out):
@instance
def logic():
while 1:
@ -126,10 +152,13 @@ def ForBreakContinueLoop(a, out):
continue
out.next = i
break
return logic
@block
def NestedForLoop1(a, out):
@instance
def logic():
while 1:
@ -141,47 +170,55 @@ def NestedForLoop1(a, out):
else:
for j in downrange(i):
if a[j] == 0:
var +=1
var += 1
break
out.next = var
return logic
@block
def NestedForLoop2(a, out):
@instance
def logic():
while 1:
yield a
var = 0
out.next = 0
for i in downrange(len(a)):
if a[i] == 0:
continue
else:
for j in downrange(i-1):
for j in downrange(i - 1):
if a[j] == 0:
pass
else:
out.next = j
break
break
return logic
def ReturnFromFunction(a):
for i in downrange(len(a)):
if a[i] == 1:
return i
return 0
for i in downrange(len(a)):
if a[i] == 1:
return i
return 0
@block
def FunctionCall(a, out):
@instance
def logic():
while 1:
yield a
out.next = ReturnFromFunction(a)
return logic
# During the following check, I noticed that non-blocking assignments
# are not scheduled when a task is disabled in Icarus. Apparently
# this is one of the many vague areas in the Verilog standard.
@ -190,10 +227,12 @@ def ReturnFromTask(a, out):
if a[i] == 1:
out[:] = i
return
out[:] = 23 # to notice it
out[:] = 23 # to notice it
@block
def TaskCall(a, out):
@instance
def logic():
var = intbv(0)[8:]
@ -201,32 +240,37 @@ def TaskCall(a, out):
yield a
ReturnFromTask(a, var)
out.next = var
return logic
@block
def WhileLoop(a, out):
@instance
def logic():
while 1:
yield a
var = 0
i = len(a)-1
i = len(a) - 1
while i >= 0:
if a[i] == 1:
var += 1
i -= 1
out.next = var
return logic
@block
def WhileContinueLoop(a, out):
@instance
def logic():
while 1:
yield a
var = 0
i = len(a)-1
i = len(a) - 1
while i >= 0:
if a[i] == 0:
i -= 1
@ -234,50 +278,56 @@ def WhileContinueLoop(a, out):
var += 1
i -= 1
out.next = var
return logic
@block
def WhileBreakLoop(a, out):
@instance
def logic():
while 1:
yield a
var = 0
i = len(a)-1
i = len(a) - 1
out.next = 0
while i >= 0:
if a[i] == 1:
out.next = i
break
i -= 1
return logic
@block
def WhileBreakContinueLoop(a, out):
@instance
def logic():
while 1:
yield a
var = 0
i = len(a)-1
i = len(a) - 1
out.next = 0
while i >= 0:
if a[i] == 0:
i -= 1
continue
i -= 1
continue
out.next = i
break
return logic
@block
def LoopTest_v(name, a, out):
return setupCosimulation(**locals())
class TestLoops(unittest.TestCase):
def bench(self, LoopTest):
a = Signal(intbv(-1)[16:])
out_v = Signal(intbv(0)[16:])
out = Signal(intbv(0)[16:])
@ -285,10 +335,10 @@ class TestLoops(unittest.TestCase):
looptest_inst = LoopTest(a, out).convert(hdl='Verilog')
# looptest_inst = LoopTest(hec, header)
looptest_v_inst = LoopTest_v(LoopTest.__name__, a, out_v)
def stimulus():
for i in range(100):
a.next = randrange(2**min(i, 16))
a.next = randrange(2 ** min(i, 16))
yield delay(10)
# print "%s %s" % (out, out_v)
self.assertEqual(out, out_v)
@ -298,47 +348,43 @@ class TestLoops(unittest.TestCase):
def testForLoop1(self):
sim = self.bench(ForLoop1)
Simulation(sim).run()
def testForLoop2(self):
sim = self.bench(ForLoop2)
Simulation(sim).run()
def testForLoop3(self):
sim = self.bench(ForLoop3)
Simulation(sim).run()
def testForLoop4(self):
sim = self.bench(ForLoop4)
Simulation(sim).run()
def testForLoop5(self):
sim = self.bench(ForLoop5)
Simulation(sim).run()
def testForLoop6(self):
sim = self.bench(ForLoop6)
Simulation(sim).run()
def testForContinueLoop(self):
sim = self.bench(ForContinueLoop)
Simulation(sim).run()
def testForBreakLoop(self):
sim = self.bench(ForBreakLoop)
Simulation(sim).run()
def testForBreakContinueLoop(self):
sim = self.bench(ForBreakContinueLoop)
Simulation(sim).run()
def testNestedForLoop1(self):
sim = self.bench(NestedForLoop1)
Simulation(sim).run()
def testNestedForLoop2(self):
sim = self.bench(NestedForLoop2)
Simulation(sim).run()
def testNestedForLoop2(self):
sim = self.bench(NestedForLoop2)
Simulation(sim).run()
@ -346,11 +392,11 @@ class TestLoops(unittest.TestCase):
def testFunctionCall(self):
sim = self.bench(FunctionCall)
Simulation(sim).run()
def testTaskCall(self):
sim = self.bench(TaskCall)
Simulation(sim).run()
def testWhileLoop(self):
sim = self.bench(WhileLoop)
Simulation(sim).run()
@ -362,11 +408,11 @@ class TestLoops(unittest.TestCase):
def testWhileBreakLoop(self):
sim = self.bench(WhileBreakLoop)
Simulation(sim).run()
def testWhileBreakContinueLoop(self):
sim = self.bench(WhileBreakContinueLoop)
Simulation(sim).run()
if __name__ == '__main__':
unittest.main()

72
myhdl/test/conversion/toVerilog/test_misc.py
View File

@ -3,31 +3,37 @@ import os
path = os.path
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instances,
instance)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
### test of constant wire support ###
# example from Frank Palazollo
@block
def or_gate(a,b,c):
def or_gate(a, b, c):
@instance
def logic():
while 1:
c.next = a | b
yield a, b
return logic
@block
def my_bundle(p,q):
def my_bundle(p, q):
r = Signal(bool(0))
gen_or = or_gate(p,r,q)
gen_or = or_gate(p, r, q)
return instances()
# additional level of hierarchy
@block
@block
def ConstWire2(p, q):
r = Signal(bool(1))
s = Signal(bool(1))
@ -35,30 +41,35 @@ def ConstWire2(p, q):
inst2 = or_gate(r, s, q)
return inst1, inst2
@block
def adder(a, b, c):
@instance
def logic():
while 1:
yield a, b
c.next = a + b
return logic
@block
@block
def ConstWire3(p, q):
t = Signal(intbv(17)[5:])
adder_inst = adder(p, t, q)
return instances()
@block
@block
def ConstWire_v(name, p, q):
return setupCosimulation(**locals())
class TestConstWires(unittest.TestCase):
def benchBool(self, ConstWire):
p = Signal(bool(0))
q = Signal(bool(0))
q_v = Signal(bool(0))
@ -67,7 +78,7 @@ class TestConstWires(unittest.TestCase):
constwire_v_inst = ConstWire_v(ConstWire.__name__, p, q_v)
def stimulus():
for i in range(100):
for dummy in range(100):
p.next = randrange(2)
yield delay(10)
self.assertEqual(q, q_v)
@ -80,10 +91,10 @@ class TestConstWires(unittest.TestCase):
def testConstWire2(self):
sim = self.benchBool(ConstWire2)
Simulation(sim).run()
Simulation(sim).run()
def benchIntbv(self, ConstWire):
p = Signal(intbv(0)[8:])
q = Signal(intbv(0)[8:])
q_v = Signal(intbv(0)[8:])
@ -96,27 +107,31 @@ class TestConstWires(unittest.TestCase):
p.next = i
yield delay(10)
self.assertEqual(q, q_v)
return stimulus(), constwire_inst, constwire_v_inst
def testConstWire3(self):
sim = self.benchIntbv(ConstWire3)
Simulation(sim).run()
### tests of code ignore facility during translation ###
@block
@block
def adderRef(a, b, c):
@instance
def logic():
while 1:
yield a, b
c.next = a + b
return logic
@block
@block
def adderDebug(a, b, c):
@instance
def logic():
while 1:
@ -124,12 +139,14 @@ def adderDebug(a, b, c):
if __debug__:
import string
c.next = a + b
return logic
def Ignorecode_v(name, a, b, c):
return setupCosimulation(**locals())
class TestIgnoreCode(unittest.TestCase):
def bench(self, adder):
@ -143,23 +160,22 @@ class TestIgnoreCode(unittest.TestCase):
ignorecode_v_inst = Ignorecode_v(adder.__name__, a, b, c_v)
def stimulus():
for i in range(100):
a.next = randrange(2**8)
b.next = randrange(2**8)
for dummy in range(100):
a.next = randrange(2 ** 8)
b.next = randrange(2 ** 8)
yield delay(10)
self.assertEqual(c, c_v)
return stimulus(), ignorecode_inst, ignorecode_v_inst
def testAdderRef(self):
sim = self.bench(adderRef)
Simulation(sim).run()
def testAdderDebug(self):
sim = self.bench(adderDebug)
Simulation(sim).run()
if __name__ == '__main__':
unittest.main()

69
myhdl/test/conversion/toVerilog/test_newcustom.py
View File

@ -7,17 +7,18 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always, always_comb,
instance, StopSimulation)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
from myhdl import ConversionError
from myhdl.conversion._misc import _error
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
@block
def incRef(count, enable, clock, reset, n):
""" Incrementer with enable.
@ -28,6 +29,7 @@ def incRef(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@instance
def logic():
while 1:
@ -37,12 +39,14 @@ def incRef(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@block
def incGen(count, enable, clock, reset, n):
""" Generator with __verilog__ is not permitted """
@instance
def logic():
incGen.verilog_code = "Template string"
@ -53,9 +57,10 @@ def incGen(count, enable, clock, reset, n):
else:
if enable:
count.next = (count + 1) % n
return logic
@block
def inc(count, enable, clock, reset, n):
""" Incrementer with enable.
@ -66,6 +71,7 @@ def inc(count, enable, clock, reset, n):
reset -- asynchronous reset input
n -- counter max value
"""
@always(clock.posedge, reset.negedge)
def incProcess():
# make it fail in conversion
@ -91,13 +97,13 @@ always @(posedge $clock, negedge $reset) begin
end
end
"""
return incProcess
@block
def incErr(count, enable, clock, reset, n):
@always(clock.posedge, reset.negedge)
def incProcess():
# make it fail in conversion
@ -123,9 +129,8 @@ always @(posedge $clock, negedge $reset) begin
end
end
"""
return incProcess
return incProcess
@block
@ -139,13 +144,14 @@ def inc_comb(nextCount, count, n):
nextCount.driven = "wire"
inc_comb.verilog_code =\
inc_comb.verilog_code = \
"""
assign $nextCount = ($count + 1) % $n;
"""
return logic
@block
def inc_seq(count, nextCount, enable, clock, reset):
@ -175,9 +181,10 @@ end
# return nothing - cannot be simulated
return []
@block
def inc2(count, enable, clock, reset, n):
nextCount = Signal(intbv(0, min=0, max=n))
comb = inc_comb(nextCount, count, n)
@ -192,28 +199,28 @@ def inc3(count, enable, clock, reset, n):
return inc2_inst
@block
def inc_v(name, count, enable, clock, reset):
return setupCosimulation(**locals())
class TestInc(TestCase):
def clockGen(self, clock):
while 1:
yield delay(10)
clock.next = not clock
def stimulus(self, enable, clock, reset):
reset.next = INACTIVE_HIGH
yield clock.negedge
reset.next = ACTIVE_LOW
yield clock.negedge
reset.next = INACTIVE_HIGH
for i in range(1000):
for dummy in range(1000):
enable.next = 1
yield clock.negedge
for i in range(1000):
for dummy in range(1000):
enable.next = min(1, randrange(5))
yield clock.negedge
raise StopSimulation
@ -231,16 +238,16 @@ class TestInc(TestCase):
# print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
self.assertEqual(count, expect)
self.assertEqual(count, count_v)
def bench(self, incRef, incVer):
m = 8
n = 2 ** m
count = Signal(intbv(0)[m:])
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for __ in range(2)]
inc_inst_ref = incRef(count, enable, clock, reset, n=n)
inc_inst = incVer(count, enable, clock, reset, n=n).convert(hdl='Verilog')
@ -257,11 +264,11 @@ class TestInc(TestCase):
""" Check increment operation """
sim = self.bench(incRef, incRef)
sim.run(quiet=1)
def testIncRefInc(self):
sim = self.bench(incRef, inc)
sim.run(quiet=1)
def testIncInc(self):
sim = self.bench(inc, inc)
sim.run(quiet=1)
@ -281,7 +288,7 @@ class TestInc(TestCase):
n = 2 ** m
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for __ in range(2)]
try:
inc_inst = incGen(count_v, enable, clock, reset, n=n).convert(hdl='Verilog')
except ConversionError as e:
@ -294,31 +301,15 @@ class TestInc(TestCase):
n = 2 ** m
count_v = Signal(intbv(0)[m:])
enable = Signal(bool(0))
clock, reset = [Signal(bool()) for i in range(2)]
clock, reset = [Signal(bool()) for _ in range(2)]
try:
inc_inst = incErr(count_v, enable, clock, reset, n=n).convert(hdl='Verilog')
except ConversionError as e:
except ConversionError:
pass
else:
self.fail()
if __name__ == '__main__':
unittest.main()

105
myhdl/test/conversion/toVerilog/test_ops.py
View File

@ -6,11 +6,12 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance, StopSimulation)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
@block
def binaryOps(
Bitand,
@ -33,6 +34,7 @@ def binaryOps(
And,
Or,
left, right):
@instance
def logic():
while 1:
@ -48,7 +50,7 @@ def binaryOps(
Mod.next = left % right
Mul.next = left * right
# Icarus doesn't support ** yet
#if left < 256 and right < 40:
# if left < 256 and right < 40:
# Pow.next = left ** right
Pow.next = 0
RightShift.next = left >> right
@ -63,8 +65,8 @@ def binaryOps(
GE.next = left >= right
And.next = bool(left) and bool(right)
Or.next = bool(left) or bool(right)
return logic
return logic
@block
@ -91,12 +93,13 @@ def binaryOps_v(name,
left, right):
return setupCosimulation(**locals())
class TestBinaryOps(TestCase):
def binaryBench(self, m, n):
M = 2**m
N = 2**n
M = 2 ** m
N = 2 ** n
left = Signal(intbv(0)[m:])
right = Signal(intbv(0)[n:])
@ -112,20 +115,20 @@ class TestBinaryOps(TestCase):
LeftShift_v = Signal(intbv(0)[64:])
Mod = Signal(intbv(0)[m:])
Mod_v = Signal(intbv(0)[m:])
Mul = Signal(intbv(0)[m+n:])
Mul_v = Signal(intbv(0)[m+n:])
Mul = Signal(intbv(0)[m + n:])
Mul_v = Signal(intbv(0)[m + n:])
Pow = Signal(intbv(0)[64:])
Pow_v = Signal(intbv(0)[64:])
RightShift = Signal(intbv(0)[m:])
RightShift_v = Signal(intbv(0)[m:])
Sub = Signal(intbv(0)[max(m, n):])
Sub_v = Signal(intbv(0)[max(m, n):])
Sum = Signal(intbv(0)[max(m, n)+1:])
Sum_v = Signal(intbv(0)[max(m, n)+1:])
EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)]
And, Or = [Signal(bool()) for i in range(2)]
And_v, Or_v, = [Signal(bool()) for i in range(2)]
Sum = Signal(intbv(0)[max(m, n) + 1:])
Sum_v = Signal(intbv(0)[max(m, n) + 1:])
EQ, NE, LT, GT, LE, GE = [Signal(bool()) for __ in range(6)]
EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for __ in range(6)]
And, Or = [Signal(bool()) for __ in range(2)]
And_v, Or_v, = [Signal(bool()) for __ in range(2)]
binops = binaryOps(
Bitand,
@ -147,7 +150,7 @@ class TestBinaryOps(TestCase):
GE,
And,
Or,
left,
left,
right).convert(hdl='Verilog')
binops_v = binaryOps_v(binaryOps.__name__,
Bitand_v,
@ -181,7 +184,7 @@ class TestBinaryOps(TestCase):
left.next = randrange(M)
right.next = randrange(N)
yield delay(10)
for j, k in ((0, 0), (0, N-1), (M-1, 0), (M-1, N-1)):
for j, k in ((0, 0), (0, N - 1), (M - 1, 0), (M - 1, N - 1)):
left.next = j
right.next = k
yield delay(10)
@ -212,13 +215,11 @@ class TestBinaryOps(TestCase):
self.assertEqual(Or, Or_v)
return binops, binops_v, stimulus(), check()
def testBinaryOps(self):
for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
sim = self.binaryBench(m, n)
Simulation(sim).run()
@block
@ -229,6 +230,7 @@ def multiOps(
And,
Or,
argm, argn, argp):
@instance
def logic():
while 1:
@ -238,11 +240,12 @@ def multiOps(
Bitxor.next = argm ^ argn ^ argp
And.next = bool(argm) and bool(argn) and bool(argp)
Or.next = bool(argm) and bool(argn) and bool(argp)
return logic
@block
def multiOps_v( name,
def multiOps_v(name,
Bitand,
Bitor,
Bitxor,
@ -252,13 +255,14 @@ def multiOps_v( name,
return setupCosimulation(**locals())
class TestMultiOps(TestCase):
def multiBench(self, m, n, p):
M = 2**m
N = 2**n
P = 2**p
M = 2 ** m
N = 2 ** n
P = 2 ** p
argm = Signal(intbv(0)[m:])
argn = Signal(intbv(0)[n:])
@ -269,8 +273,8 @@ class TestMultiOps(TestCase):
Bitor_v = Signal(intbv(0)[max(m, n, p):])
Bitxor = Signal(intbv(0)[max(m, n, p):])
Bitxor_v = Signal(intbv(0)[max(m, n, p):])
And, Or = [Signal(bool()) for i in range(2)]
And_v, Or_v, = [Signal(bool()) for i in range(2)]
And, Or = [Signal(bool()) for __ in range(2)]
And_v, Or_v, = [Signal(bool()) for __ in range(2)]
multiops = multiOps(
Bitand,
@ -278,8 +282,8 @@ class TestMultiOps(TestCase):
Bitxor,
And,
Or,
argm,
argn,
argm,
argn,
argp).convert(hdl='Verilog')
multiops_v = multiOps_v(multiOps.__name__,
Bitand_v,
@ -301,9 +305,9 @@ class TestMultiOps(TestCase):
argn.next = randrange(N)
argp.next = randrange(P)
yield delay(10)
for j, k, l in ((0, 0, 0), (0, 0, P-1), (0, N-1, P-1),
(M-1, 0, 0), (M-1, 0, P-1), (M-1, N-1, 0),
(0, N-1, 0), (M-1, N-1, P-1)):
for j, k, l in ((0, 0, 0), (0, 0, P - 1), (0, N - 1, P - 1),
(M - 1, 0, 0), (M - 1, 0, P - 1), (M - 1, N - 1, 0),
(0, N - 1, 0), (M - 1, N - 1, P - 1)):
argm.next = j
argn.next = k
argp.next = l
@ -321,7 +325,6 @@ class TestMultiOps(TestCase):
self.assertEqual(Or, Or_v)
return multiops, multiops_v, stimulus(), check()
def testMultiOps(self):
for m, n, p in ((4, 4, 4,), (5, 3, 2), (3, 4, 6), (3, 7, 4)):
@ -329,7 +332,6 @@ class TestMultiOps(TestCase):
Simulation(sim).run()
@block
def unaryOps(
Not,
@ -337,6 +339,7 @@ def unaryOps(
UnaryAdd,
UnarySub,
arg):
@instance
def logic():
while 1:
@ -344,25 +347,21 @@ def unaryOps(
Not.next = not arg
Invert.next = ~arg
UnaryAdd.next = +arg
UnarySub.next = --arg
UnarySub.next = - -arg
return logic
@block
def unaryOps_v(name,
Not,
Invert,
UnaryAdd,
UnarySub,
arg):
return setupCosimulation(**locals())
@block
def unaryOps_v(name, Not, Invert, UnaryAdd, UnarySub, arg):
return setupCosimulation(**locals())
class TestUnaryOps(TestCase):
def unaryBench(self, m):
M = 2**m
M = 2 ** m
arg = Signal(intbv(0)[m:])
Not = Signal(bool(0))
@ -426,6 +425,7 @@ def augmOps(
Sub,
Sum,
left, right):
@instance
def logic():
var = intbv(0)[max(64, len(left) + len(right)):]
@ -465,11 +465,12 @@ def augmOps(
var[:] = left
var += right
Sum.next = var
return logic
@block
def augmOps_v( name,
def augmOps_v(name,
Bitand,
Bitor,
Bitxor,
@ -483,12 +484,13 @@ def augmOps_v( name,
left, right):
return setupCosimulation(**locals())
class TestAugmOps(TestCase):
def augmBench(self, m, n):
M = 2**m
N = 2**n
M = 2 ** m
N = 2 ** n
left = Signal(intbv(0)[m:])
right = Signal(intbv(0)[n:])
@ -504,14 +506,14 @@ class TestAugmOps(TestCase):
LeftShift_v = Signal(intbv(0)[64:])
Mod = Signal(intbv(0)[m:])
Mod_v = Signal(intbv(0)[m:])
Mul = Signal(intbv(0)[m+n:])
Mul_v = Signal(intbv(0)[m+n:])
Mul = Signal(intbv(0)[m + n:])
Mul_v = Signal(intbv(0)[m + n:])
RightShift = Signal(intbv(0)[m:])
RightShift_v = Signal(intbv(0)[m:])
Sub = Signal(intbv(0)[max(m, n):])
Sub_v = Signal(intbv(0)[max(m, n):])
Sum = Signal(intbv(0)[max(m, n)+1:])
Sum_v = Signal(intbv(0)[max(m, n)+1:])
Sum = Signal(intbv(0)[max(m, n) + 1:])
Sum_v = Signal(intbv(0)[max(m, n) + 1:])
augmops = augmOps(
Bitand,
@ -525,7 +527,7 @@ class TestAugmOps(TestCase):
Sub,
Sum,
left, right).convert(hdl='Verilog')
augmops_v = augmOps_v( augmOps.__name__,
augmops_v = augmOps_v(augmOps.__name__,
Bitand_v,
Bitor_v,
Bitxor_v,
@ -548,7 +550,7 @@ class TestAugmOps(TestCase):
left.next = randrange(M)
right.next = randrange(N)
yield delay(10)
for j, k in ((0, 0), (0, N-1), (M-1, 0), (M-1, N-1)):
for j, k in ((0, 0), (0, N - 1), (M - 1, 0), (M - 1, N - 1)):
left.next = j
right.next = k
yield delay(10)
@ -570,14 +572,13 @@ class TestAugmOps(TestCase):
self.assertEqual(Sum, Sum_v)
return augmops, augmops_v, stimulus(), check()
def testAugmOps(self):
for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
sim = self.augmBench(m, n)
Simulation(sim).run()
if __name__ == '__main__':
unittest.main()

65
myhdl/test/conversion/toVerilog/test_ram.py
View File

@ -3,37 +3,35 @@ path = os.path
import unittest
from unittest import TestCase
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, always, always_comb,
instance, StopSimulation)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
@block
def ram(dout, din, addr, we, clk, depth=128):
""" Simple ram model """
@instance
def logic():
mem = [intbv(0)[8:] for i in range(depth)]
a = intbv(0)[8:]
mem = [intbv(0)[8:] for dummy in range(depth)]
# ad = 1
while 1:
yield clk.posedge
if we:
ad = int(addr)
mem[int(addr)][:] = din
# a = din.val
# a[2] = din
dout.next = mem[int(addr)]
return logic
@block
def ram_clocked(dout, din, addr, we, clk, depth=128):
""" Ram model """
mem = [Signal(intbv(0)[8:]) for i in range(depth)]
mem = [Signal(intbv(0)[8:]) for __ in range(depth)]
@instance
def access():
@ -42,14 +40,15 @@ def ram_clocked(dout, din, addr, we, clk, depth=128):
if we:
mem[int(addr)].next = din
dout.next = mem[int(addr)]
return access
@block
def ram_deco1(dout, din, addr, we, clk, depth=128):
""" Ram model """
mem = [Signal(intbv(0)[8:]) for i in range(depth)]
mem = [Signal(intbv(0)[8:]) for __ in range(depth)]
@instance
def write():
@ -57,24 +56,25 @@ def ram_deco1(dout, din, addr, we, clk, depth=128):
yield clk.posedge
if we:
mem[int(addr)].next = din
@always_comb
def read():
dout.next = mem[int(addr)]
return write, read
@block
def ram_deco2(dout, din, addr, we, clk, depth=128):
""" Ram model """
mem = [Signal(intbv(0)[8:]) for i in range(depth)]
mem = [Signal(intbv(0)[8:]) for __ in range(depth)]
@always(clk.posedge)
def write():
if we:
mem[int(addr)].next = din
@always_comb
def read():
dout.next = mem[int(addr)]
@ -82,33 +82,33 @@ def ram_deco2(dout, din, addr, we, clk, depth=128):
return write, read
@block
def ram2(dout, din, addr, we, clk, depth=128):
# memL = [intbv(0,min=dout._min,max=dout._max) for i in range(depth)]
memL = [Signal(intbv()[len(dout):]) for i in range(depth)]
memL = [Signal(intbv()[len(dout):]) for __ in range(depth)]
@instance
def wrLogic() :
def wrLogic():
while 1:
yield clk.posedge
if we:
memL[int(addr)].next = din
@instance
def rdLogic() :
def rdLogic():
while 1:
yield clk.posedge
dout.next = memL[int(addr)]
return wrLogic, rdLogic
@block
def ram_v(name, dout, din, addr, we, clk, depth=4):
return setupCosimulation(**locals())
class TestMemory(TestCase):
def bench(self, ram, depth=128):
@ -135,8 +135,8 @@ class TestMemory(TestCase):
yield clk.negedge
yield clk.posedge
yield delay(1)
#print dout
#print dout_v
# print dout
# print dout_v
self.assertEqual(dout, i)
# self.assertEqual(dout, dout_v)
raise StopSimulation()
@ -151,25 +151,24 @@ class TestMemory(TestCase):
def test1(self):
sim = self.bench(ram)
Simulation(sim).run()
def test2(self):
sim = self.bench(ram2)
Simulation(sim).run()
def testram_clocked(self):
sim = self.bench(ram_clocked)
Simulation(sim).run()
def testram_deco1(self):
sim = self.bench(ram_deco1)
Simulation(sim).run()
def testram_deco2(self):
sim = self.bench(ram_deco2)
Simulation(sim).run()
if __name__ == '__main__':
unittest.main()

29
myhdl/test/conversion/toVerilog/test_rom.py
View File

@ -4,34 +4,36 @@ import unittest
from unittest import TestCase
from random import randrange
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance, always_comb, StopSimulation)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
D = 256
ROM = tuple([randrange(D) for i in range(D)])
ROM = tuple([randrange(D) for __ in range(D)])
# ROM = [randrange(256) for i in range(256)]
@block
def rom1(dout, addr, clk):
@instance
def rdLogic() :
def rdLogic():
while 1:
yield clk.posedge
dout.next = ROM[int(addr)]
return rdLogic
@block
def rom2(dout, addr, clk):
theROM = ROM
@instance
def rdLogic() :
def rdLogic():
while 1:
yield clk.posedge
dout.next = theROM[int(addr)]
@ -43,7 +45,7 @@ def rom2(dout, addr, clk):
def rom3(dout, addr, clk):
@instance
def rdLogic() :
def rdLogic():
tmp = intbv(0)[8:]
while 1:
yield addr
@ -52,6 +54,7 @@ def rom3(dout, addr, clk):
return rdLogic
@block
def rom4(dout, addr, clk):
@ -61,10 +64,12 @@ def rom4(dout, addr, clk):
return read
@block
def rom_v(name, dout, addr, clk):
return setupCosimulation(**locals())
class TestRom(TestCase):
def bench(self, rom):
@ -97,22 +102,20 @@ class TestRom(TestCase):
def test1(self):
sim = self.bench(rom1)
Simulation(sim).run()
def test2(self):
sim = self.bench(rom2)
Simulation(sim).run()
def test3(self):
sim = self.bench(rom3)
Simulation(sim).run()
def test4(self):
sim = self.bench(rom4)
Simulation(sim).run()
if __name__ == '__main__':
unittest.main()

343
myhdl/test/conversion/toVerilog/test_signed.py
View File

@ -6,22 +6,22 @@ import random
from random import randrange
random.seed(2)
import myhdl
from myhdl import *
from myhdl import (block, Signal, intbv, delay, instance, always, StopSimulation)
from myhdl._Simulation import Simulation
from .util import setupCosimulation
@block
def binaryOps(
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
# # Bitand,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
## Mod,
# # Mod,
Mul,
## Pow,
# # Pow,
RightShift,
Sub,
Sum, Sum1, Sum2, Sum3,
@ -39,23 +39,23 @@ def binaryOps(
def logic():
while 1:
yield left, right
## Bitand.next = left & right
## Bitor.next = left | right
## Bitxor.next = left ^ right
## if right != 0:
## FloorDiv.next = left // right
# # Bitand.next = left & right
# # Bitor.next = left | right
# # Bitxor.next = left ^ right
# # if right != 0:
# # FloorDiv.next = left // right
if left < 256 and right < 40 and right >= 0:
LeftShift.next = left << right
## if right != 0:
## Mod.next = left % right
# # if right != 0:
# # Mod.next = left % right
Mul.next = left * right
## # Icarus doesn't support ** yet
## #if left < 256 and right < 40:
## # Pow.next = left ** right
## Pow.next = 0
# # # Icarus doesn't support ** yet
# # #if left < 256 and right < 40:
# # # Pow.next = left ** right
# # Pow.next = 0
if right >= -0:
RightShift.next = left >> right
## RightShift.next = left
RightShift.next = left >> right
# # RightShift.next = left
Sub.next = left - right
Sum.next = left + right
Sum1.next = left + right[2:]
@ -75,14 +75,14 @@ def binaryOps(
@block
def binaryOps_v(name,
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
# # Bitand,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
## Mod,
# # Mod,
Mul,
## Pow,
# # Pow,
RightShift,
Sub,
Sum, Sum1, Sum2, Sum3,
@ -97,6 +97,7 @@ def binaryOps_v(name,
left, right, bit):
return setupCosimulation(**locals())
class TestBinaryOps(TestCase):
def binaryBench(self, Ll, Ml, Lr, Mr):
@ -104,43 +105,43 @@ class TestBinaryOps(TestCase):
bit = Signal(bool(0))
left = Signal(intbv(Ll, min=Ll, max=Ml))
right = Signal(intbv(Lr, min=Lr, max=Mr))
M = 2**14
## Bitand = Signal(intbv(0, min=-2**17, max=2**17))
## Bitand_v = Signal(intbv(0, min=-2**17, max=2**17))
## Bitor = Signal(intbv(0)[max(m, n):])
## Bitor_v = Signal(intbv(0)[max(m, n):])
## Bitxor = Signal(intbv(0)[max(m, n):])
## Bitxor_v = Signal(intbv(0)[max(m, n):])
## FloorDiv = Signal(intbv(0)[m:])
## FloorDiv_v = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
LeftShift_v = Signal(intbv(0, min=-2**64, max=2**64))
## Mod = Signal(intbv(0)[m:])
## Mod_v = Signal(intbv(0)[m:])
Mul = Signal(intbv(0, min=-2**17, max=2**17))
Mul_v = Signal(intbv(0, min=-2**17, max=2**17))
## Pow = Signal(intbv(0)[64:])
## Pow_v = Signal(intbv(0)[64:])
M = 2 ** 14
# # Bitand = Signal(intbv(0, min=-2**17, max=2**17))
# # Bitand_v = Signal(intbv(0, min=-2**17, max=2**17))
# # Bitor = Signal(intbv(0)[max(m, n):])
# # Bitor_v = Signal(intbv(0)[max(m, n):])
# # Bitxor = Signal(intbv(0)[max(m, n):])
# # Bitxor_v = Signal(intbv(0)[max(m, n):])
# # FloorDiv = Signal(intbv(0)[m:])
# # FloorDiv_v = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0, min=-2 ** 64, max=2 ** 64))
LeftShift_v = Signal(intbv(0, min=-2 ** 64, max=2 ** 64))
# # Mod = Signal(intbv(0)[m:])
# # Mod_v = Signal(intbv(0)[m:])
Mul = Signal(intbv(0, min=-2 ** 17, max=2 ** 17))
Mul_v = Signal(intbv(0, min=-2 ** 17, max=2 ** 17))
# # Pow = Signal(intbv(0)[64:])
# # Pow_v = Signal(intbv(0)[64:])
RightShift = Signal(intbv(0, min=-M, max=M))
RightShift_v = Signal(intbv(0, min=-M, max=M))
Sub, Sub1, Sub2, Sub3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
Sub_v, Sub1_v, Sub2_v, Sub3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)]
Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
Sum_v, Sum1_v, Sum2_v, Sum3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)]
EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)]
And, Or = [Signal(bool()) for i in range(2)]
And_v, Or_v, = [Signal(bool()) for i in range(2)]
Sub = Signal(intbv(min=-M, max=M))
Sub_v = Signal(intbv(min=-M, max=M))
Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for __ in range(4)]
Sum_v, Sum1_v, Sum2_v, Sum3_v = [Signal(intbv(min=-M, max=M)) for __ in range(4)]
EQ, NE, LT, GT, LE, GE = [Signal(bool()) for __ in range(6)]
EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for __ in range(6)]
And, Or = [Signal(bool()) for __ in range(2)]
And_v, Or_v, = [Signal(bool()) for __ in range(2)]
binops = binaryOps(
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
# # Bitand,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
## Mod,
# # Mod,
Mul,
## Pow,
# # Pow,
RightShift,
Sub,
Sum, Sum1, Sum2, Sum3,
@ -154,14 +155,14 @@ class TestBinaryOps(TestCase):
Or,
left, right, bit).convert(hdl='Verilog')
binops_v = binaryOps_v(binaryOps.__name__,
## Bitand_v,
## Bitor_v,
## Bitxor_v,
## FloorDiv_v,
# # Bitand_v,
# # Bitor_v,
# # Bitxor_v,
# # FloorDiv_v,
LeftShift_v,
## Mod_v,
# # Mod_v,
Mul_v,
## Pow_v,
# # Pow_v,
RightShift_v,
Sub_v,
Sum_v, Sum1_v, Sum2_v, Sum3_v,
@ -176,12 +177,12 @@ class TestBinaryOps(TestCase):
left, right, bit)
def stimulus():
for i in range(100):
for dummy in range(100):
# bit.next = False
left.next = randrange(Ll, Ml)
right.next = randrange(Lr, Mr)
yield delay(10)
for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
for j, k in ((Ll, Lr), (Ml - 1, Mr - 1), (Ll, Mr - 1), (Ml - 1, Lr)):
left.next = j
right.next = k
yield delay(10)
@ -191,27 +192,27 @@ class TestBinaryOps(TestCase):
yield left, right
bit.next = not bit
yield delay(1)
#print "%s %s %s %s" % (left, right, Mul, Mul_v)
#print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v))
#print "%s %s %s %s" % (left, right, Sum, Sum_v)
#print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v))
## print left
## print right
## print bin(left)
## print bin(right)
## print bin(Bitand)
## print bin(Bitand_v)
## print Bitand
## print Bitand_v
## self.assertEqual(Bitand, Bitand_v)
#w = len(Bitand)
#self.assertEqual(bin(Bitand, w), bin(Bitand_v,w ))
## self.assertEqual(Bitor, Bitor_v)
## self.assertEqual(Bitxor, Bitxor_v)
## self.assertEqual(FloorDiv, FloorDiv_v)
# print "%s %s %s %s" % (left, right, Mul, Mul_v)
# print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v))
# print "%s %s %s %s" % (left, right, Sum, Sum_v)
# print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v))
# # print left
# # print right
# # print bin(left)
# # print bin(right)
# # print bin(Bitand)
# # print bin(Bitand_v)
# # print Bitand
# # print Bitand_v
# # self.assertEqual(Bitand, Bitand_v)
# w = len(Bitand)
# self.assertEqual(bin(Bitand, w), bin(Bitand_v,w ))
# # self.assertEqual(Bitor, Bitor_v)
# # self.assertEqual(Bitxor, Bitxor_v)
# # self.assertEqual(FloorDiv, FloorDiv_v)
self.assertEqual(LeftShift, LeftShift_v)
## self.assertEqual(Mod, Mod_v)
# # self.assertEqual(Mod, Mod_v)
self.assertEqual(Mul, Mul_v)
# self.assertEqual(Pow, Pow_v)
self.assertEqual(RightShift, RightShift_v)
@ -230,7 +231,6 @@ class TestBinaryOps(TestCase):
self.assertEqual(Or, Or_v)
return binops, binops_v, stimulus(), check()
def testBinaryOps(self):
for Ll, Ml, Lr, Mr in (
@ -246,7 +246,6 @@ class TestBinaryOps(TestCase):
Simulation(sim).run()
@block
def unaryOps(
Not,
@ -262,7 +261,7 @@ def unaryOps(
Not.next = not arg
Invert.next = ~arg
UnaryAdd.next = +arg
UnarySub.next = --arg
UnarySub.next = - -arg
return logic
@ -273,15 +272,14 @@ def unaryOps_v(name,
UnaryAdd,
UnarySub,
arg):
return setupCosimulation(**locals())
return setupCosimulation(**locals())
class TestUnaryOps(TestCase):
def unaryBench(self, m):
M = 2**m
M = 2 ** m
arg = Signal(intbv(0, min=-M, max=+M))
Not = Signal(bool(0))
@ -334,12 +332,12 @@ class TestUnaryOps(TestCase):
@block
def augmOps(
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
# # Bitand,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
## Mod,
# # Mod,
Mul,
RightShift,
Sub,
@ -348,31 +346,31 @@ def augmOps(
@instance
def logic():
var = intbv(0, min=-2**17, max=+2**17)
var2 = intbv(0, min=-2**64, max=+2**64)
var = intbv(0, min=-2 ** 17, max=+2 ** 17)
var2 = intbv(0, min=-2 ** 64, max=+2 ** 64)
while 1:
yield left, right
## var[:] = left
## var &= right
## Bitand.next = var
## var[:] = left
## var |= right
## Bitor.next = var
## var[:] = left
## var ^= left
## Bitxor.next = var
## if right != 0:
## var[:] = left
## var //= right
## FloorDiv.next = var
# # var[:] = left
# # var &= right
# # Bitand.next = var
# # var[:] = left
# # var |= right
# # Bitor.next = var
# # var[:] = left
# # var ^= left
# # Bitxor.next = var
# # if right != 0:
# # var[:] = left
# # var //= right
# # FloorDiv.next = var
if left < 256 and right < 40 and right >= 0:
var2[:] = left
var2 <<= right
LeftShift.next = var2
## if right != 0:
## var[:] = left
## var %= right
## Mod.next = var
# # if right != 0:
# # var[:] = left
# # var %= right
# # Mod.next = var
var[:] = left
var *= right
Mul.next = var
@ -391,14 +389,15 @@ def augmOps(
return logic
@block
def augmOps_v( name,
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
def augmOps_v(name,
# # Bitand,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
## Mod,
# # Mod,
Mul,
RightShift,
Sub,
@ -406,33 +405,32 @@ def augmOps_v( name,
left, right):
return setupCosimulation(**locals())
class TestAugmOps(TestCase):
def augmBench(self, Ll, Ml, Lr, Mr):
left = Signal(intbv(Ll, min=Ll, max=Ml))
right = Signal(intbv(Lr, min=Lr, max=Mr))
M = 2**17
M = 2 ** 17
# # Bitand = Signal(intbv(0)[max(m, n):])
# # Bitand_v = Signal(intbv(0)[max(m, n):])
# # Bitor = Signal(intbv(0)[max(m, n):])
# # Bitor_v = Signal(intbv(0)[max(m, n):])
# # Bitxor = Signal(intbv(0)[max(m, n):])
# # Bitxor_v = Signal(intbv(0)[max(m, n):])
# # FloorDiv = Signal(intbv(0)[m:])
# # FloorDiv_v = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0, min=-2 ** 64, max=2 ** 64))
LeftShift_v = Signal(intbv(0, min=-2 ** 64, max=2 ** 64))
# # Mod = Signal(intbv(0)[m:])
# # Mod_v = Signal(intbv(0)[m:])
## Bitand = Signal(intbv(0)[max(m, n):])
## Bitand_v = Signal(intbv(0)[max(m, n):])
## Bitor = Signal(intbv(0)[max(m, n):])
## Bitor_v = Signal(intbv(0)[max(m, n):])
## Bitxor = Signal(intbv(0)[max(m, n):])
## Bitxor_v = Signal(intbv(0)[max(m, n):])
## FloorDiv = Signal(intbv(0)[m:])
## FloorDiv_v = Signal(intbv(0)[m:])
LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
LeftShift_v = Signal(intbv(0, min=-2**64, max=2**64))
## Mod = Signal(intbv(0)[m:])
## Mod_v = Signal(intbv(0)[m:])
Mul = Signal(intbv(0, min=-M, max=+M))
Mul_v = Signal(intbv(0, min=-M, max=+M))
RightShift = Signal(intbv(0, min=-M, max=+M))
RightShift_v = Signal(intbv(0, min=-M, max=+M))
@ -442,25 +440,25 @@ class TestAugmOps(TestCase):
Sum_v = Signal(intbv(0, min=-M, max=+M))
augmops = augmOps(
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
# # Bitand,
# # Bitor,
# # Bitxor,
# # FloorDiv,
LeftShift,
## Mod,
# # Mod,
Mul,
RightShift,
Sub,
Sum,
left,
left,
right).convert(hdl='Verilog')
augmops_v = augmOps_v( augmOps.__name__,
## Bitand_v,
## Bitor_v,
## Bitxor_v,
## FloorDiv_v,
augmops_v = augmOps_v(augmOps.__name__,
# # Bitand_v,
# # Bitor_v,
# # Bitxor_v,
# # FloorDiv_v,
LeftShift_v,
## Mod_v,
# # Mod_v,
Mul_v,
RightShift_v,
Sub_v,
@ -468,11 +466,11 @@ class TestAugmOps(TestCase):
left, right)
def stimulus():
for i in range(100):
for dummy in range(100):
left.next = randrange(Ll, Ml)
right.next = randrange(Lr, Mr)
yield delay(10)
for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
for j, k in ((Ll, Lr), (Ml - 1, Mr - 1), (Ll, Mr - 1), (Ml - 1, Lr)):
left.next = j
right.next = k
yield delay(10)
@ -482,22 +480,21 @@ class TestAugmOps(TestCase):
yield left, right
yield delay(1)
# print "%s %s %s %s" % (left, right, Or, Or_v)
## self.assertEqual(Bitand, Bitand_v)
## self.assertEqual(Bitor, Bitor_v)
## self.assertEqual(Bitxor, Bitxor_v)
## self.assertEqual(FloorDiv, FloorDiv_v)
## self.assertEqual(LeftShift, LeftShift_v)
## self.assertEqual(Mod, Mod_v)
# # self.assertEqual(Bitand, Bitand_v)
# # self.assertEqual(Bitor, Bitor_v)
# # self.assertEqual(Bitxor, Bitxor_v)
# # self.assertEqual(FloorDiv, FloorDiv_v)
# # self.assertEqual(LeftShift, LeftShift_v)
# # self.assertEqual(Mod, Mod_v)
self.assertEqual(Mul, Mul_v)
self.assertEqual(RightShift, RightShift_v)
self.assertEqual(Sub, Sub_v)
self.assertEqual(Sum, Sum_v)
return augmops, augmops_v, stimulus(), check()
def testAugmOps(self):
for Ll, Ml, Lr, Mr in (
for Ll, Ml, Lr, Mr in (
(-254, 236, 0, 4),
(-128, 128, -128, 128),
(-53, 25, -23, 123),
@ -509,11 +506,11 @@ class TestAugmOps(TestCase):
sim = self.augmBench(Ll, Ml, Lr, Mr)
Simulation(sim).run()
@block
def expressions(a, b, clk):
c = Signal(intbv(0, min=0, max=47))
e = Signal(bool())
@instance
def logic():
@ -553,26 +550,26 @@ def expressions(a, b, clk):
a.next = ~c + 1
b.next = ~d + 1
yield clk.posedge
raise StopSimulation
return logic
@block
@block
def expressions_v(a, b, clk):
return setupCosimulation(**locals())
return setupCosimulation(**locals())
class TestExpressions(TestCase):
@block
def bench(self):
a, a_v = [Signal(intbv(0, min=-34, max=47)) for i in range(2)]
b, b_v = [Signal(intbv(0, min=0, max=47)) for i in range(2)]
a, a_v = [Signal(intbv(0, min=-34, max=47)) for __ in range(2)]
b, b_v = [Signal(intbv(0, min=0, max=47)) for __ in range(2)]
clk = Signal(bool())
expr = expressions(a, b, clk).convert(hdl='Verilog')
expr_v = expressions(a_v, b_v, clk).convert(hdl='Verilog')
@ -591,14 +588,12 @@ class TestExpressions(TestCase):
clk.next = not clk
return expr, expr_v, check, clkgen
def testExpressions(self):
sim = self.bench()
Simulation(sim).run()
if __name__ == '__main__':
unittest.main()

2
myhdl/test/conversion/toVerilog/test_tristate.py
View File

@ -1,4 +1,3 @@
import os
import pytest
import unittest
@ -30,6 +29,7 @@ class OBuf(object):
def interface(self):
return self.A, self.Y, self.OE
@block
def tristate_obuf_i(obuf):
'''three-state output buffer, using interface'''

17
myhdl/test/conversion/toVerilog2/test_loops.py
View File

@ -2,13 +2,14 @@ import os
path = os.path
from random import randrange
import myhdl
from myhdl import *
from myhdl.conversion import verify, analyze
from myhdl import (Signal, intbv, delay, instance)
from myhdl.conversion import analyze
from myhdl import ConversionError
from myhdl.conversion._misc import _error
def ForLoopError1(a, out):
@instance
def logic():
while 1:
@ -18,15 +19,17 @@ def ForLoopError1(a, out):
if a[i] == 1:
var += 1
out.next = var
return logic
def LoopBench(LoopTest):
a = Signal(intbv(-1)[16:])
z = Signal(intbv(0)[16:])
looptest_inst = LoopTest(a, z)
data = tuple([randrange(2**min(i, 16)) for i in range(100)])
data = tuple([randrange(2 ** min(i, 16)) for i in range(100)])
@instance
def stimulus():
@ -36,7 +39,7 @@ def LoopBench(LoopTest):
print(z)
return stimulus, looptest_inst
def testForLoopError1():
try:
@ -45,6 +48,4 @@ def testForLoopError1():
assert e.kind == _error.Requirement
else:
assert False

2
myhdl/test/core/test_Cosimulation.py
View File

@ -36,7 +36,6 @@ random.seed(1) # random, but deterministic
MAXLINE = 4096
exe = "python {0} ".format(os.path.abspath(__file__))
fromSignames = ['a', 'bb', 'ccc']
@ -256,5 +255,6 @@ class TestCosimulation:
buf += " "
os.write(wt, buf.encode())
if __name__ == "__main__":
getattr(TestCosimulation, sys.argv[1])()

58
myhdl/test/core/test_ShadowSignal.py
View File

@ -1,16 +1,16 @@
import myhdl
from myhdl import *
from myhdl import (Signal, intbv, instance, delay, ConcatSignal, TristateSignal)
from myhdl._Simulation import Simulation
def bench_SliceSignal():
s = Signal(intbv(0)[8:])
a, b, c = s(7), s(5), s(0)
d, e, f, g = s(8,5), s(6,3), s(8,0), s(4,3)
d, e, f, g = s(8, 5), s(6, 3), s(8, 0), s(4, 3)
@instance
def check():
for i in range(2**len(s)):
for i in range(2 ** len(s)):
s.next = i
yield delay(10)
assert s[7] == a
@ -27,16 +27,17 @@ def bench_SliceSignal():
def test_SliceSignal():
Simulation(bench_SliceSignal()).run()
def bench_SliceSlicedSignal():
s = Signal(intbv(0)[8:])
a, b = s(8,4), s(4,0)
aa, ab = a(4,2), a(2,0)
ba, bb = b(4,2), b(2,0)
a, b = s(8, 4), s(4, 0)
aa, ab = a(4, 2), a(2, 0)
ba, bb = b(4, 2), b(2, 0)
@instance
def check():
for i in range(2**len(s)):
for i in range(2 ** len(s)):
s.next = i
yield delay(10)
assert s[8:6] == aa
@ -50,6 +51,7 @@ def bench_SliceSlicedSignal():
def test_SliceSlicedSignal():
Simulation(bench_SliceSlicedSignal()).run()
def bench_ConcatSignal():
a = Signal(intbv(0)[5:])
@ -61,10 +63,10 @@ def bench_ConcatSignal():
@instance
def check():
for i in range(2**len(a)):
for i in range(2 ** len(a)):
for j in (0, 1):
for k in range(2**len(c)):
for m in range(2**len(d)):
for k in range(2 ** len(c)):
for m in range(2 ** len(d)):
a.next = i
b.next = j
c.next = k
@ -100,11 +102,11 @@ def bench_ConcatSignalWithConsts():
@instance
def check():
for i in range(2**len(a)):
for i in range(2 ** len(a)):
for j in (0, 1):
for k in range(2**len(c)):
for m in range(2**len(d)):
for n in range(2**len(e)):
for k in range(2 ** len(c)):
for m in range(2 ** len(d)):
for n in range(2 ** len(e)):
a.next = i
b.next = j
c.next = k
@ -128,11 +130,12 @@ def bench_ConcatSignalWithConsts():
def test_ConcatSignalWithConsts():
Simulation(bench_ConcatSignalWithConsts()).run()
def bench_ConcatSignalWithNegs():
Am = 2**(5-1)
Cm = 2**(3-1)
Dm = 2**(4-1)
Am = 2 ** (5 - 1)
Cm = 2 ** (3 - 1)
Dm = 2 ** (4 - 1)
a = Signal(intbv(-1, min=-Am, max=Am))
b = Signal(bool(0))
@ -152,7 +155,7 @@ def bench_ConcatSignalWithNegs():
c.next = k
d.next = m
yield delay(10)
assert s[13:8] == a[len(a):]
assert s[7] == b
assert s[7:4] == c[len(c):]
@ -160,6 +163,7 @@ def bench_ConcatSignalWithNegs():
return check
def test_ConcatSignalWithNegs():
Simulation(bench_ConcatSignalWithNegs()).run()
@ -168,20 +172,20 @@ def bench_ConcatConcatedSignal():
aa = Signal(intbv(0)[2:0])
ab = Signal(intbv(0)[2:0])
a = ConcatSignal(aa,ab)
a = ConcatSignal(aa, ab)
ba = Signal(intbv(0)[2:0])
bb = Signal(intbv(0)[2:0])
b = ConcatSignal(ba,bb)
b = ConcatSignal(ba, bb)
s = ConcatSignal(a,b)
s = ConcatSignal(a, b)
@instance
def check():
for iaa in range(2**len(aa)):
for iab in range(2**len(ab)):
for iba in range(2**len(ba)):
for ibb in range(2**len(bb)):
for iaa in range(2 ** len(aa)):
for iab in range(2 ** len(ab)):
for iba in range(2 ** len(ba)):
for ibb in range(2 ** len(bb)):
aa.next = iaa
ab.next = iab
ba.next = iba
@ -191,12 +195,14 @@ def bench_ConcatConcatedSignal():
assert s[6:4] == ab
assert s[4:2] == ba
assert s[2:0] == bb
return check
def test_ConcatConcatedSignal():
Simulation(bench_ConcatConcatedSignal()).run()
def bench_TristateSignal():
s = TristateSignal(intbv(0)[8:])
a = s.driver()

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