From f18a2664bf624782f975be9fbe34959ae16488e0 Mon Sep 17 00:00:00 2001 From: Jan Decaluwe Date: Sat, 22 Nov 2008 22:40:25 +0100 Subject: [PATCH] Added conversion examples from manual --- example/manual/FramerCtrl.v | 69 +++++++++++++++ example/manual/FramerCtrl.vhd | 79 +++++++++++++++++ example/manual/GrayInc.py | 55 ++++++++++++ example/manual/GrayIncReg.v | 50 +++++++++++ example/manual/GrayIncReg.vhd | 57 ++++++++++++ example/manual/Inc.v | 34 +++++++ example/manual/Inc.vhd | 38 ++++++++ example/manual/bin2gray.v | 29 ++++++ example/manual/bin2gray.vhd | 35 ++++++++ example/manual/custom.py | 51 +++++++++++ example/manual/inc_comb.v | 23 +++++ example/manual/inc_comb.vhd | 29 ++++++ example/manual/pck_myhdl_06dev10.vhd | 128 +++++++++++++++++++++++++++ example/manual/ram.vhd | 42 +++++++++ example/manual/ram_1.v | 35 ++++++++ example/manual/rom.v | 29 ++++++ example/manual/rom.vhd | 35 ++++++++ example/manual/run_all.py | 2 + example/manual/tb_FramerCtrl.v | 29 ++++++ example/manual/tb_GrayIncReg.v | 26 ++++++ example/manual/tb_Inc.v | 26 ++++++ example/manual/tb_bin2gray.v | 20 +++++ example/manual/tb_inc_comb.v | 20 +++++ example/manual/tb_ram_1.v | 29 ++++++ example/manual/tb_rom.v | 20 +++++ 25 files changed, 990 insertions(+) create mode 100644 example/manual/FramerCtrl.v create mode 100644 example/manual/FramerCtrl.vhd create mode 100644 example/manual/GrayInc.py create mode 100644 example/manual/GrayIncReg.v create mode 100644 example/manual/GrayIncReg.vhd create mode 100644 example/manual/Inc.v create mode 100644 example/manual/Inc.vhd create mode 100644 example/manual/bin2gray.v create mode 100644 example/manual/bin2gray.vhd create mode 100644 example/manual/custom.py create mode 100644 example/manual/inc_comb.v create mode 100644 example/manual/inc_comb.vhd create mode 100644 example/manual/pck_myhdl_06dev10.vhd create mode 100644 example/manual/ram.vhd create mode 100644 example/manual/ram_1.v create mode 100644 example/manual/rom.v create mode 100644 example/manual/rom.vhd create mode 100644 example/manual/tb_FramerCtrl.v create mode 100644 example/manual/tb_GrayIncReg.v create mode 100644 example/manual/tb_Inc.v create mode 100644 example/manual/tb_bin2gray.v create mode 100644 example/manual/tb_inc_comb.v create mode 100644 example/manual/tb_ram_1.v create mode 100644 example/manual/tb_rom.v diff --git a/example/manual/FramerCtrl.v b/example/manual/FramerCtrl.v new file mode 100644 index 00000000..26bd8676 --- /dev/null +++ b/example/manual/FramerCtrl.v @@ -0,0 +1,69 @@ +// File: FramerCtrl.v +// Generated by MyHDL 0.6dev10 +// Date: Sat Nov 22 22:39:38 2008 + +`timescale 1ns/10ps + +module FramerCtrl ( + SOF, + state, + syncFlag, + clk, + reset_n +); + +output SOF; +reg SOF; +output [2:0] state; +reg [2:0] state; +input syncFlag; +input clk; +input reset_n; + +reg [7:0] index; + + + +always @(posedge clk, negedge reset_n) begin: FRAMERCTRL_FSM + if ((reset_n == 0)) begin + SOF <= 0; + index <= 0; + state <= 3'b001; + end + else begin + index <= ((index + 1) % 8); + SOF <= 0; + // synthesis parallel_case full_case + casez (state) + 3'b??1: begin + index <= 1; + if (syncFlag) begin + state <= 3'b010; + end + end + 3'b?1?: begin + if ((index == 0)) begin + if (syncFlag) begin + state <= 3'b100; + end + else begin + state <= 3'b001; + end + end + end + 3'b1??: begin + if ((index == 0)) begin + if ((!syncFlag)) begin + state <= 3'b001; + end + end + SOF <= (index == (8 - 1)); + end + default: begin + $finish; + end + endcase + end +end + +endmodule diff --git a/example/manual/FramerCtrl.vhd b/example/manual/FramerCtrl.vhd new file mode 100644 index 00000000..1629ddfe --- /dev/null +++ b/example/manual/FramerCtrl.vhd @@ -0,0 +1,79 @@ +-- File: FramerCtrl.vhd +-- Generated by MyHDL 0.6dev10 +-- Date: Sat Nov 22 22:39:38 2008 + + +package pck_FramerCtrl is + + type t_enum_t_State_1 is ( + SEARCH, + CONFIRM, + SYNC +); +attribute enum_encoding of t_enum_t_State_1: type is "001 010 100"; + +end package pck_FramerCtrl; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use std.textio.all; + +use work.pck_myhdl_06dev10.all; + +use work.pck_FramerCtrl.all; + +entity FramerCtrl is + port ( + SOF: out std_logic; + state: inout t_enum_t_State_1; + syncFlag: in std_logic; + clk: in std_logic; + reset_n: in std_logic + ); +end entity FramerCtrl; + +architecture MyHDL of FramerCtrl is + +signal index: unsigned(7 downto 0); + +begin + + +FRAMERCTRL_FSM: process (clk, reset_n) is +begin + if (reset_n = '0') then + SOF <= '0'; + index <= "00000000"; + state <= SEARCH; + elsif rising_edge(clk) then + index <= ((index + 1) mod 8); + SOF <= '0'; + case state is + when SEARCH => + index <= "00000001"; + if to_boolean(syncFlag) then + state <= CONFIRM; + end if; + when CONFIRM => + if (index = 0) then + if to_boolean(syncFlag) then + state <= SYNC; + else + state <= SEARCH; + end if; + end if; + when SYNC => + if (index = 0) then + if (not to_boolean(syncFlag)) then + state <= SEARCH; + end if; + end if; + SOF <= to_std_logic(signed(resize(index, 9)) = (8 - 1)); + when others => + assert False report "End of Simulation" severity Failure; + end case; + end if; +end process FRAMERCTRL_FSM; + +end architecture MyHDL; diff --git a/example/manual/GrayInc.py b/example/manual/GrayInc.py new file mode 100644 index 00000000..eb2a6749 --- /dev/null +++ b/example/manual/GrayInc.py @@ -0,0 +1,55 @@ +from myhdl import * + +from bin2gray2 import bin2gray +from inc import Inc + +def GrayInc(graycnt, enable, clock, reset, width): + + bincnt = Signal(intbv(0)[width:]) + + inc_1 = Inc(bincnt, enable, clock, reset, n=2**width) + bin2gray_1 = bin2gray(B=bincnt, G=graycnt, width=width) + + return inc_1, bin2gray_1 + + +def GrayIncReg(graycnt, enable, clock, reset, width): + + graycnt_comb = Signal(intbv(0)[width:]) + + gray_inc_1 = GrayInc(graycnt_comb, enable, clock, reset, width) + + @always(clock.posedge) + def reg_1(): + graycnt.next = graycnt_comb + + return gray_inc_1, reg_1 + + +def main(): + width = 8 + graycnt = Signal(intbv(0)[width:]) + enable, clock, reset = [Signal(bool()) for i in range(3)] + toVerilog(GrayIncReg, graycnt, enable, clock, reset, width) + toVHDL(GrayIncReg, graycnt, enable, clock, reset, width) + + +if __name__ == '__main__': + main() + + + + + + + + + + + + + + + + + diff --git a/example/manual/GrayIncReg.v b/example/manual/GrayIncReg.v new file mode 100644 index 00000000..18b8d30d --- /dev/null +++ b/example/manual/GrayIncReg.v @@ -0,0 +1,50 @@ +// File: GrayIncReg.v +// Generated by MyHDL 0.6dev10 +// Date: Sat Nov 22 22:39:37 2008 + +`timescale 1ns/10ps + +module GrayIncReg ( + graycnt, + enable, + clock, + reset +); + +output [7:0] graycnt; +reg [7:0] graycnt; +input enable; +input clock; +input reset; + +reg [7:0] graycnt_comb; +reg [7:0] gray_inc_1_bincnt; + + + +always @(posedge clock, negedge reset) begin: GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC + if ((reset == 0)) begin + gray_inc_1_bincnt <= 0; + end + else begin + if (enable) begin + gray_inc_1_bincnt <= ((gray_inc_1_bincnt + 1) % 256); + end + end +end + +always @(gray_inc_1_bincnt) begin: GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC + integer i; + reg [9-1:0] Bext; + Bext = 9'h0; + Bext = gray_inc_1_bincnt; + for (i=0; i<8; i=i+1) begin + graycnt_comb[i] <= (Bext[(i + 1)] ^ Bext[i]); + end +end + +always @(posedge clock) begin: GRAYINCREG_REG_1 + graycnt <= graycnt_comb; +end + +endmodule diff --git a/example/manual/GrayIncReg.vhd b/example/manual/GrayIncReg.vhd new file mode 100644 index 00000000..2e1c6a76 --- /dev/null +++ b/example/manual/GrayIncReg.vhd @@ -0,0 +1,57 @@ +-- File: GrayIncReg.vhd +-- Generated by MyHDL 0.6dev10 +-- Date: Sat Nov 22 22:39:37 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use std.textio.all; + +use work.pck_myhdl_06dev10.all; + +entity GrayIncReg is + port ( + graycnt: out unsigned(7 downto 0); + enable: in std_logic; + clock: in std_logic; + reset: in std_logic + ); +end entity GrayIncReg; + +architecture MyHDL of GrayIncReg is + +signal graycnt_comb: unsigned(7 downto 0); +signal gray_inc_1_bincnt: unsigned(7 downto 0); + +begin + + +GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is +begin + if (reset = '0') then + gray_inc_1_bincnt <= "00000000"; + elsif rising_edge(clock) then + if to_boolean(enable) then + gray_inc_1_bincnt <= ((gray_inc_1_bincnt + 1) mod 256); + end if; + end if; +end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC; + +GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is + variable Bext: unsigned(8 downto 0); +begin + Bext := to_unsigned(0, 9); + Bext := resize(gray_inc_1_bincnt, 9); + for i in 0 to 8-1 loop + graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i)); + end loop; +end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC; + +GRAYINCREG_REG_1: process (clock) is +begin + if rising_edge(clock) then + graycnt <= graycnt_comb; + end if; +end process GRAYINCREG_REG_1; + +end architecture MyHDL; diff --git a/example/manual/Inc.v b/example/manual/Inc.v new file mode 100644 index 00000000..5c80ad54 --- /dev/null +++ b/example/manual/Inc.v @@ -0,0 +1,34 @@ +// File: Inc.v +// Generated by MyHDL 0.6dev10 +// Date: Sat Nov 22 22:39:37 2008 + +`timescale 1ns/10ps + +module Inc ( + count, + enable, + clock, + reset +); + +output [7:0] count; +reg [7:0] count; +input enable; +input clock; +input reset; + + + + +always @(posedge clock, negedge reset) begin: INC_INCLOGIC + if ((reset == 0)) begin + count <= 0; + end + else begin + if (enable) begin + count <= ((count + 1) % 256); + end + end +end + +endmodule diff --git a/example/manual/Inc.vhd b/example/manual/Inc.vhd new file mode 100644 index 00000000..6654bcfe --- /dev/null +++ b/example/manual/Inc.vhd @@ -0,0 +1,38 @@ +-- File: Inc.vhd +-- Generated by MyHDL 0.6dev10 +-- Date: Sat Nov 22 22:39:37 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use std.textio.all; + +use work.pck_myhdl_06dev10.all; + +entity Inc is + port ( + count: inout unsigned(7 downto 0); + enable: in std_logic; + clock: in std_logic; + reset: in std_logic + ); +end entity Inc; + +architecture MyHDL of Inc is + + +begin + + +INC_INCLOGIC: process (clock, reset) is +begin + if (reset = '0') then + count <= "00000000"; + elsif rising_edge(clock) then + if to_boolean(enable) then + count <= ((count + 1) mod 256); + end if; + end if; +end process INC_INCLOGIC; + +end architecture MyHDL; diff --git a/example/manual/bin2gray.v b/example/manual/bin2gray.v new file mode 100644 index 00000000..9df3ddef --- /dev/null +++ b/example/manual/bin2gray.v @@ -0,0 +1,29 @@ +// File: bin2gray.v +// Generated by MyHDL 0.6dev10 +// Date: Sat Nov 22 22:39:37 2008 + +`timescale 1ns/10ps + +module bin2gray ( + B, + G +); + +input [7:0] B; +output [7:0] G; +reg [7:0] G; + + + + +always @(B) begin: BIN2GRAY_LOGIC + integer i; + reg [9-1:0] Bext; + Bext = 9'h0; + Bext = B; + for (i=0; i<8; i=i+1) begin + G[i] <= (Bext[(i + 1)] ^ Bext[i]); + end +end + +endmodule diff --git a/example/manual/bin2gray.vhd b/example/manual/bin2gray.vhd new file mode 100644 index 00000000..f23f06f2 --- /dev/null +++ b/example/manual/bin2gray.vhd @@ -0,0 +1,35 @@ +-- File: bin2gray.vhd +-- Generated by MyHDL 0.6dev10 +-- Date: Sat Nov 22 22:39:37 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use std.textio.all; + +use work.pck_myhdl_06dev10.all; + +entity bin2gray is + port ( + B: in unsigned(7 downto 0); + G: out unsigned(7 downto 0) + ); +end entity bin2gray; + +architecture MyHDL of bin2gray is + + +begin + + +BIN2GRAY_LOGIC: process (B) is + variable Bext: unsigned(8 downto 0); +begin + Bext := to_unsigned(0, 9); + Bext := resize(B, 9); + for i in 0 to 8-1 loop + G(i) <= (Bext((i + 1)) xor Bext(i)); + end loop; +end process BIN2GRAY_LOGIC; + +end architecture MyHDL; diff --git a/example/manual/custom.py b/example/manual/custom.py new file mode 100644 index 00000000..4e529a08 --- /dev/null +++ b/example/manual/custom.py @@ -0,0 +1,51 @@ +from myhdl import * + +def inc_comb(nextCount, count, n): + + @always(count) + def logic(): + # do nothing here + pass + + nextCount.driven = "wire" + + __verilog__ =\ +""" +assign %(nextCount)s = (%(count)s + 1) %% %(n)s; +""" + + __vhdl__ =\ +""" +%(nextCount)s <= (%(count)s + 1) mod %(n)s; +""" + + return logic + + + +def main(): + m = 8 + n = 2 ** m + count = Signal(intbv(0)[m:]) + nextCount = Signal(intbv(0)[m:]) + toVerilog(inc_comb, nextCount, count, n) + toVHDL(inc_comb, nextCount, count, n) + + +if __name__ == '__main__': + main() + + + + + + + + + + + + + + + diff --git a/example/manual/inc_comb.v b/example/manual/inc_comb.v new file mode 100644 index 00000000..a6debf41 --- /dev/null +++ b/example/manual/inc_comb.v @@ -0,0 +1,23 @@ +// File: inc_comb.v +// Generated by MyHDL 0.6dev10 +// Date: Sat Nov 22 22:39:38 2008 + +`timescale 1ns/10ps + +module inc_comb ( + nextCount, + count +); + +output [7:0] nextCount; +wire [7:0] nextCount; +input [7:0] count; + + + + + + +assign nextCount = (count + 1) % 256; + +endmodule diff --git a/example/manual/inc_comb.vhd b/example/manual/inc_comb.vhd new file mode 100644 index 00000000..fbf922d2 --- /dev/null +++ b/example/manual/inc_comb.vhd @@ -0,0 +1,29 @@ +-- File: inc_comb.vhd +-- Generated by MyHDL 0.6dev10 +-- Date: Sat Nov 22 22:39:38 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use std.textio.all; + +use work.pck_myhdl_06dev10.all; + +entity inc_comb is + port ( + nextCount: out unsigned(7 downto 0); + count: in unsigned(7 downto 0) + ); +end entity inc_comb; + +architecture MyHDL of inc_comb is + + +begin + + + + +nextCount <= (count + 1) mod 256; + +end architecture MyHDL; diff --git a/example/manual/pck_myhdl_06dev10.vhd b/example/manual/pck_myhdl_06dev10.vhd new file mode 100644 index 00000000..7c8eec12 --- /dev/null +++ b/example/manual/pck_myhdl_06dev10.vhd @@ -0,0 +1,128 @@ +-- File: pck_myhdl_06dev10.vhd +-- Generated by MyHDL 0.6dev10 +-- Date: Sat Nov 22 22:39:37 2008 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pck_myhdl_06dev10 is + + attribute enum_encoding: string; + + function to_std_logic (arg: boolean) return std_logic; + + function to_unsigned (arg: boolean; size: natural) return unsigned; + + function to_signed (arg: boolean; size: natural) return signed; + + function to_integer(arg: boolean) return integer; + + function to_integer(arg: std_logic) return integer; + + function to_unsigned (arg: std_logic; size: natural) return unsigned; + + function to_signed (arg: std_logic; size: natural) return signed; + + function to_boolean (arg: std_logic) return boolean; + + function to_boolean (arg: unsigned) return boolean; + + function to_boolean (arg: signed) return boolean; + + function to_boolean (arg: integer) return boolean; + + function "-" (arg: unsigned) return signed; + +end pck_myhdl_06dev10; + + +package body pck_myhdl_06dev10 is + + function to_std_logic (arg: boolean) return std_logic is + begin + if arg then + return '1'; + else + return '0'; + end if; + end function to_std_logic; + + function to_unsigned (arg: boolean; size: natural) return unsigned is + variable res: unsigned(size-1 downto 0) := (others => '0'); + begin + if arg then + res(0):= '1'; + end if; + return res; + end function to_unsigned; + + function to_signed (arg: boolean; size: natural) return signed is + variable res: signed(size-1 downto 0) := (others => '0'); + begin + if arg then + res(0) := '1'; + end if; + return res; + end function to_signed; + + function to_integer(arg: boolean) return integer is + begin + if arg then + return 1; + else + return 0; + end if; + end function to_integer; + + function to_integer(arg: std_logic) return integer is + begin + if arg = '1' then + return 1; + else + return 0; + end if; + end function to_integer; + + function to_unsigned (arg: std_logic; size: natural) return unsigned is + variable res: unsigned(size-1 downto 0) := (others => '0'); + begin + res(0):= arg; + return res; + end function to_unsigned; + + function to_signed (arg: std_logic; size: natural) return signed is + variable res: signed(size-1 downto 0) := (others => '0'); + begin + res(0) := arg; + return res; + end function to_signed; + + function to_boolean (arg: std_logic) return boolean is + begin + return arg = '1'; + end function to_boolean; + + function to_boolean (arg: unsigned) return boolean is + begin + return arg /= 0; + end function to_boolean; + + function to_boolean (arg: signed) return boolean is + begin + return arg /= 0; + end function to_boolean; + + function to_boolean (arg: integer) return boolean is + begin + return arg /= 0; + end function to_boolean; + + function "-" (arg: unsigned) return signed is + begin + return - signed(resize(arg, arg'length+1)); + end function "-"; + +end pck_myhdl_06dev10; + + diff --git a/example/manual/ram.vhd b/example/manual/ram.vhd new file mode 100644 index 00000000..3fffbac9 --- /dev/null +++ b/example/manual/ram.vhd @@ -0,0 +1,42 @@ +-- File: ram.vhd +-- Generated by MyHDL 0.6dev10 +-- Date: Sat Nov 22 22:39:38 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use std.textio.all; + +use work.pck_myhdl_06dev10.all; + +entity ram is + port ( + dout: out unsigned(7 downto 0); + din: in unsigned(7 downto 0); + addr: in unsigned(6 downto 0); + we: in std_logic; + clk: in std_logic + ); +end entity ram; + +architecture MyHDL of ram is + +type t_array_mem is array(0 to 128-1) of unsigned(7 downto 0); +signal mem: t_array_mem; + +begin + + +RAM_WRITE: process (clk) is +begin + if rising_edge(clk) then + if to_boolean(we) then + mem(to_integer(addr)) <= din; + end if; + end if; +end process RAM_WRITE; + + +dout <= mem(to_integer(addr)); + +end architecture MyHDL; diff --git a/example/manual/ram_1.v b/example/manual/ram_1.v new file mode 100644 index 00000000..d6c91c9d --- /dev/null +++ b/example/manual/ram_1.v @@ -0,0 +1,35 @@ +// File: ram_1.v +// Generated by MyHDL 0.6dev10 +// Date: Sat Nov 22 22:39:38 2008 + +`timescale 1ns/10ps + +module ram_1 ( + dout, + din, + addr, + we, + clk +); + +output [7:0] dout; +wire [7:0] dout; +input [7:0] din; +input [6:0] addr; +input we; +input clk; + + +reg [7:0] mem [0:128-1]; + + +always @(posedge clk) begin: RAM_1_WRITE + if (we) begin + mem[addr] <= din; + end +end + + +assign dout = mem[addr]; + +endmodule diff --git a/example/manual/rom.v b/example/manual/rom.v new file mode 100644 index 00000000..dada2fef --- /dev/null +++ b/example/manual/rom.v @@ -0,0 +1,29 @@ +// File: rom.v +// Generated by MyHDL 0.6dev10 +// Date: Sat Nov 22 22:39:38 2008 + +`timescale 1ns/10ps + +module rom ( + dout, + addr +); + +output [7:0] dout; +reg [7:0] dout; +input [3:0] addr; + + + + +always @(addr) begin: ROM_READ + // synthesis parallel_case full_case + case (addr) + 0: dout <= 17; + 1: dout <= 134; + 2: dout <= 52; + default: dout <= 9; + endcase +end + +endmodule diff --git a/example/manual/rom.vhd b/example/manual/rom.vhd new file mode 100644 index 00000000..fd1e34c1 --- /dev/null +++ b/example/manual/rom.vhd @@ -0,0 +1,35 @@ +-- File: rom.vhd +-- Generated by MyHDL 0.6dev10 +-- Date: Sat Nov 22 22:39:38 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use std.textio.all; + +use work.pck_myhdl_06dev10.all; + +entity rom is + port ( + dout: out unsigned(7 downto 0); + addr: in unsigned(3 downto 0) + ); +end entity rom; + +architecture MyHDL of rom is + + +begin + + +ROM_READ: process (addr) is +begin + case to_integer(addr) is + when 0 => dout <= "00010001"; + when 1 => dout <= "10000110"; + when 2 => dout <= "00110100"; + when others => dout <= "00001001"; + end case; +end process ROM_READ; + +end architecture MyHDL; diff --git a/example/manual/run_all.py b/example/manual/run_all.py index 6253b4e5..4a4f435d 100644 --- a/example/manual/run_all.py +++ b/example/manual/run_all.py @@ -3,6 +3,7 @@ modules = ('hello1', 'greetings', 'bin2gray', 'bin2gray2', + 'GrayInc', 'hec', 'rs232', 'mux', @@ -16,6 +17,7 @@ modules = ('hello1', 'fifo', 'rom', 'ram', + 'custom', ) for n in modules: diff --git a/example/manual/tb_FramerCtrl.v b/example/manual/tb_FramerCtrl.v new file mode 100644 index 00000000..fb16a16e --- /dev/null +++ b/example/manual/tb_FramerCtrl.v @@ -0,0 +1,29 @@ +module tb_FramerCtrl; + +wire SOF; +wire [2:0] state; +reg syncFlag; +reg clk; +reg reset_n; + +initial begin + $from_myhdl( + syncFlag, + clk, + reset_n + ); + $to_myhdl( + SOF, + state + ); +end + +FramerCtrl dut( + SOF, + state, + syncFlag, + clk, + reset_n +); + +endmodule diff --git a/example/manual/tb_GrayIncReg.v b/example/manual/tb_GrayIncReg.v new file mode 100644 index 00000000..9a3e843e --- /dev/null +++ b/example/manual/tb_GrayIncReg.v @@ -0,0 +1,26 @@ +module tb_GrayIncReg; + +wire [7:0] graycnt; +reg enable; +reg clock; +reg reset; + +initial begin + $from_myhdl( + enable, + clock, + reset + ); + $to_myhdl( + graycnt + ); +end + +GrayIncReg dut( + graycnt, + enable, + clock, + reset +); + +endmodule diff --git a/example/manual/tb_Inc.v b/example/manual/tb_Inc.v new file mode 100644 index 00000000..4ed37081 --- /dev/null +++ b/example/manual/tb_Inc.v @@ -0,0 +1,26 @@ +module tb_Inc; + +wire [7:0] count; +reg enable; +reg clock; +reg reset; + +initial begin + $from_myhdl( + enable, + clock, + reset + ); + $to_myhdl( + count + ); +end + +Inc dut( + count, + enable, + clock, + reset +); + +endmodule diff --git a/example/manual/tb_bin2gray.v b/example/manual/tb_bin2gray.v new file mode 100644 index 00000000..8d8f0f47 --- /dev/null +++ b/example/manual/tb_bin2gray.v @@ -0,0 +1,20 @@ +module tb_bin2gray; + +reg [7:0] B; +wire [7:0] G; + +initial begin + $from_myhdl( + B + ); + $to_myhdl( + G + ); +end + +bin2gray dut( + B, + G +); + +endmodule diff --git a/example/manual/tb_inc_comb.v b/example/manual/tb_inc_comb.v new file mode 100644 index 00000000..7be701ce --- /dev/null +++ b/example/manual/tb_inc_comb.v @@ -0,0 +1,20 @@ +module tb_inc_comb; + +wire [7:0] nextCount; +reg [7:0] count; + +initial begin + $from_myhdl( + count + ); + $to_myhdl( + nextCount + ); +end + +inc_comb dut( + nextCount, + count +); + +endmodule diff --git a/example/manual/tb_ram_1.v b/example/manual/tb_ram_1.v new file mode 100644 index 00000000..38b1c66d --- /dev/null +++ b/example/manual/tb_ram_1.v @@ -0,0 +1,29 @@ +module tb_ram_1; + +wire [7:0] dout; +reg [7:0] din; +reg [6:0] addr; +reg we; +reg clk; + +initial begin + $from_myhdl( + din, + addr, + we, + clk + ); + $to_myhdl( + dout + ); +end + +ram_1 dut( + dout, + din, + addr, + we, + clk +); + +endmodule diff --git a/example/manual/tb_rom.v b/example/manual/tb_rom.v new file mode 100644 index 00000000..3f98eb19 --- /dev/null +++ b/example/manual/tb_rom.v @@ -0,0 +1,20 @@ +module tb_rom; + +wire [7:0] dout; +reg [3:0] addr; + +initial begin + $from_myhdl( + addr + ); + $to_myhdl( + dout + ); +end + +rom dut( + dout, + addr +); + +endmodule