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Add vhdl_/verilog_instance to _Block decorator

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This commit is contained in:
Bruno Kremel 2016-08-04 14:21:28 +02:00
parent 310abe82ce
commit f19f1e3caf
1 changed files with 8 additions and 1 deletions
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9
myhdl/_block.py
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@ -31,7 +31,8 @@ from myhdl import BlockError, BlockInstanceError, Cosimulation
from myhdl._instance import _Instantiator
from myhdl._util import _flatten
from myhdl._extractHierarchy import (_makeMemInfo,
_UserVerilogCode, _UserVhdlCode)
_UserVerilogCode, _UserVhdlCode,
_UserVerilogInstance, _UserVhdlInstance)
from myhdl._Signal import _Signal, _isListOfSigs
@ -166,6 +167,12 @@ class _Block(object):
if hasattr(deco, 'vhdl_code'):
self.vhdl_code = _UserVhdlCode(deco.vhdl_code, self.symdict, func.__name__,
func, srcfile, srcline)
if hasattr(deco, 'verilog_instance'):
self.verilog_code = _UserVerilogInstance(deco.vhdl_instance, self.symdict, func.__name__,
func, srcfile, srcline)
if hasattr(deco, 'vhdl_instance'):
self.vhdl_code = _UserVhdlInstance(deco.vhdl_instance, self.symdict, func.__name__,
func, srcfile, srcline)
self._config_sim = {'trace': False}
def _verifySubs(self):