From 01da49766ef4b97802d04b60c9b282dc144a582e Mon Sep 17 00:00:00 2001 From: iamsrinivas Date: Mon, 6 Apr 2015 22:58:56 -0500 Subject: [PATCH 1/2] test_always_seq.py Added new test to increase the coverage of the code. The tests do not reach the full coverage(100%). We need to extend this test to improve the coverage hence forward using this test. --- myhdl/test/core2/test_always_seq.py | 54 +++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 myhdl/test/core2/test_always_seq.py diff --git a/myhdl/test/core2/test_always_seq.py b/myhdl/test/core2/test_always_seq.py new file mode 100644 index 00000000..95fdfafb --- /dev/null +++ b/myhdl/test/core2/test_always_seq.py @@ -0,0 +1,54 @@ +from random import randrange +from pytest import raises +from myhdl import * + +from myhdl import Signal, Simulation, instances, now + +from myhdl._always_seq import always_seq, _AlwaysSeq, _error, AlwaysSeqError + + + +def test_clock(): + """ check the edge parameter """ + + # should fail without a valid Signal + clock = Signal(bool(0)) + reset = ResetSignal(0, active=0, async=True) + + with raises(AlwaysSeqError) as e: + @always_seq(clock, reset=reset) + def logic1(): + pass + assert e.kind == _error.EdgeType + + # should work with a valid Signal + clock = Signal(bool(0)) + try: + @always_seq(clock.posedge, reset=reset) + def logic2(): + pass + except: + pytest.fail() + +def test_reset(): + """ check the reset parameter """ + + # should fail without a valid ResetSignal + clock = Signal(bool(0)) + reset = Signal(bool(0)) + + with raises(AlwaysSeqError): + @always_seq(clock.posedge, reset=reset) + def logic(): + pass + assert e.kind == _error.ResetType + + # should work with a valid Signal + reset = ResetSignal(0, active=0, async=True) + try: + @always_seq(clock.posedge, reset=reset) + def logic2(): + pass + except: + pytest.fail() + From 6fe06849a47fe6026c4604fd4e64c35c654ac53a Mon Sep 17 00:00:00 2001 From: iamsrinivas Date: Fri, 17 Apr 2015 11:10:16 -0500 Subject: [PATCH 2/2] Update test_always_seq.py Fixed bugs --- myhdl/test/core2/test_always_seq.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/myhdl/test/core2/test_always_seq.py b/myhdl/test/core2/test_always_seq.py index 95fdfafb..1506ac0c 100644 --- a/myhdl/test/core2/test_always_seq.py +++ b/myhdl/test/core2/test_always_seq.py @@ -28,7 +28,7 @@ def test_clock(): def logic2(): pass except: - pytest.fail() + assert False def test_reset(): """ check the reset parameter """ @@ -37,7 +37,7 @@ def test_reset(): clock = Signal(bool(0)) reset = Signal(bool(0)) - with raises(AlwaysSeqError): + with raises(AlwaysSeqError) as e: @always_seq(clock.posedge, reset=reset) def logic(): pass @@ -50,5 +50,5 @@ def test_reset(): def logic2(): pass except: - pytest.fail() + assert False