mirror of
https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
Loads of changes
This commit is contained in:
jand
parent
bf9b8212ac
commit
f39b616069
@ -40,6 +40,7 @@ from myhdl import ToVerilogError
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from myhdl._extractHierarchy import _HierExtr, _findInstanceName
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from myhdl._util import _flatten
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from myhdl._unparse import _unparse
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from myhdl._cell_deref import _cell_deref
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_converting = 0
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_profileFunc = None
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@ -328,7 +329,9 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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ast.vardict = {}
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ast.inputs = Set()
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ast.outputs = Set()
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ast.argnames = []
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ast.kind = None
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ast.isTask = False
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self.ast = ast
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self.labelStack = []
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self.refStack = ReferenceStack()
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@ -387,6 +390,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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node.obj = int()
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def visitAssAttr(self, node, access=OUTPUT, *args):
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self.ast.isTask = True
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self.visit(node.expr, OUTPUT)
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def visitAssign(self, node, access=OUTPUT, *args):
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@ -451,11 +455,17 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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s = inspect.getsource(func)
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s = s.lstrip()
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ast = compiler.parse(s)
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# print ast
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print ast
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ast.name = genLabel.next() + "_" + func.__name__
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ast.sourcefile = inspect.getsourcefile(func)
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ast.lineoffset = inspect.getsourcelines(func)[1]-1
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ast.symdict = func.func_globals.copy()
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# handle free variables
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if func.func_code.co_freevars:
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for n, c in zip(func.func_code.co_freevars, func.func_closure):
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obj = _cell_deref(c)
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assert isinstance(obj, (int, long, Signal))
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ast.symdict[n] = obj
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v = _NotSupportedVisitor(ast)
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compiler.walk(ast, v)
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v = _AnalyzeFuncVisitor(ast, node.args)
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@ -535,6 +545,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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if access == INPUT:
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self.ast.inputs.add(n)
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elif access == OUTPUT:
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self.ast.isTask = True
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self.ast.outputs.add(n)
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elif access == UNKNOWN:
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pass
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@ -639,7 +650,6 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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def __init__(self, ast, args):
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_AnalyzeVisitor.__init__(self, ast)
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self.args = args
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self.ast.argnames = []
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self.ast.hasReturn = False
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self.ast.returnObj = None
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@ -818,6 +828,7 @@ def _convertGens(genlist, vfile):
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vfile.write(funcBuf.getvalue()); funcBuf.close()
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vfile.write(blockBuf.getvalue()); blockBuf.close()
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YIELD, PRINT = range(2)
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class _ConvertVisitor(_ToVerilogMixin):
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@ -826,7 +837,6 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.buf = buf
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self.returnLabel = ast.name
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self.ind = ''
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self.inYield = False
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self.isSigAss = False
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self.labelStack = []
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@ -842,11 +852,14 @@ class _ConvertVisitor(_ToVerilogMixin):
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if type(obj) is bool:
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self.write("%s%s;" % (dir, name))
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elif isinstance(obj, int):
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if dir == "input ":
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self.write("input %s;" % name)
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self.writeline()
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self.write("integer %s;" % name)
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elif hasattr(obj, '_nrbits'):
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self.write("%s[%s-1:0] %s;" % (dir, obj._nrbits, name))
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else:
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raise AssertionError("unexpected type")
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raise AssertionError("var %s has unexpected type %s" % (name, type(obj)))
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def writeDeclarations(self):
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for name, obj in self.ast.vardict.items():
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@ -865,21 +878,26 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.write(" %s " % op)
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self.visit(node.right)
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self.write(")")
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def visitAdd(self, node):
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def visitAdd(self, node, *args):
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self.binaryOp(node, '+')
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def visitFloorDiv(self, node):
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def visitFloorDiv(self, node, *args):
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self.binaryOp(node, '/')
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def visitLeftShift(self, node):
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def visitLeftShift(self, node, *args):
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self.binaryOp(node, '<<')
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def visitMod(self, node):
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self.binaryOp(node, '%')
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def visitMul(self, node):
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def visitMod(self, node, context=None, *args):
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if context == PRINT:
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self.visit(node.left)
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self.write(", ")
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self.visit(node.right)
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else:
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self.binaryOp(node, '%')
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def visitMul(self, node, *args):
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self.binaryOp(node, '*')
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def visitPower(self, node):
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def visitPower(self, node, *args):
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self.binaryOp(node, '**')
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def visitSub(self, node):
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def visitSub(self, node, *args):
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self.binaryOp(node, "-")
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def visitRightShift(self, node):
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def visitRightShift(self, node, *args):
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self.binaryOp(node, '>>')
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def multiOp(self, node, op):
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@ -889,41 +907,41 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.write(" %s " % op)
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self.visit(node)
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self.write(")")
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def visitAnd(self, node):
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def visitAnd(self, node, *args):
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self.multiOp(node, '&&')
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def visitBitand(self, node):
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def visitBitand(self, node, *args):
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self.multiOp(node, '&')
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def visitBitor(self, node):
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def visitBitor(self, node, *args):
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self.multiOp(node, '|')
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def visitBitxor(self, node):
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def visitBitxor(self, node, *args):
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self.multiOp(node, '^')
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def visitOr(self, node):
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def visitOr(self, node, *args):
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self.multiOp(node, '||')
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def unaryOp(self, node, op):
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self.write("(%s" % op)
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self.visit(node.expr)
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self.write(")")
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def visitInvert(self, node):
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def visitInvert(self, node, *args):
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self.unaryOp(node, '~')
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def visitNot(self, node):
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def visitNot(self, node, *args):
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self.unaryOp(node, '!')
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def visitUnaryAdd(self, node, *args):
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self.unaryOp(node, '+')
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def visitUnarySub(self, node, *args):
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self.unaryOp(node, '-')
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def visitAssAttr(self, node):
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def visitAssAttr(self, node, *args):
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if node.attrname != 'next':
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self.raiseError(node, _error.NotSupported, "attribute assignment")
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self.isSigAss = True
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self.visit(node.expr)
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def visitAssert(self, node):
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def visitAssert(self, node, *args):
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# XXX
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pass
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def visitAssign(self, node):
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def visitAssign(self, node, *args):
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assert len(node.nodes) == 1
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self.visit(node.nodes[0])
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if self.isSigAss:
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@ -934,10 +952,10 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.visit(node.expr)
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self.write(';')
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def visitAssName(self, node):
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def visitAssName(self, node, *args):
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self.write(node.name)
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def visitAugAssign(self, node):
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def visitAugAssign(self, node, *args):
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opmap = {"+=" : "+",
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"-=" : "-",
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"*=" : "*",
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@ -961,10 +979,10 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.visit(node.expr)
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self.write(";")
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def visitBreak(self, node):
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def visitBreak(self, node, *args):
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self.write("disable %s;" % self.labelStack[-2])
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def visitCallFunc(self, node):
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def visitCallFunc(self, node, *args):
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fn = node.node
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assert isinstance(fn, astNode.Name)
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f = self.getObj(fn)
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@ -981,29 +999,28 @@ class _ConvertVisitor(_ToVerilogMixin):
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return
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elif type(f) in (ClassType, type) and issubclass(f, Exception):
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self.write(f.__name__)
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self.write(": ")
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elif f is concat:
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opening, closing = '{', '}'
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elif hasattr(node, 'ast'):
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self.write(node.ast.name)
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else:
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self.write(f.__name__)
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self.write(opening)
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if node.args:
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self.write(opening)
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self.visit(node.args[0])
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for arg in node.args[1:]:
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self.write(", ")
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self.visit(arg)
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self.write(closing)
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self.write(closing)
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if hasattr(node, 'ast'):
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if node.ast.outputs:
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if node.ast.isTask:
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Visitor = _ConvertTaskVisitor
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else:
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Visitor = _ConvertFunctionVisitor
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v = Visitor(node.ast, self.funcBuf)
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compiler.walk(node.ast, v)
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def visitCompare(self, node):
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def visitCompare(self, node, *args):
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self.write("(")
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self.visit(node.expr)
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op, code = node.ops[0]
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@ -1011,20 +1028,24 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.visit(code)
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self.write(")")
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def visitConst(self, node):
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self.write(node.value)
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def visitConst(self, node, context=None, *args):
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if context == PRINT:
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assert type(node.value) is str
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self.write('"Verilog %s"' % node.value)
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else:
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self.write(node.value)
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def visitContinue(self, node):
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def visitContinue(self, node, *args):
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self.write("disable %s;" % self.labelStack[-1])
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def visitDiscard(self, node):
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def visitDiscard(self, node, *args):
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expr = node.expr
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self.visit(expr)
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# ugly hack to detect an orphan "task" call
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if isinstance(expr, astNode.CallFunc) and hasattr(expr, 'ast'):
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self.write(';')
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def visitFor(self, node):
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def visitFor(self, node, *args):
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self.labelStack.append(node.breakLabel)
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self.labelStack.append(node.loopLabel)
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var = node.assign.name
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@ -1086,10 +1107,10 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.labelStack.pop()
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self.labelStack.pop()
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def visitFunction(self, node):
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def visitFunction(self, node, *args):
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raise AssertionError("To be implemented in subclass")
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def visitGetattr(self, node):
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def visitGetattr(self, node, *args):
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assert isinstance(node.expr, astNode.Name)
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assert node.expr.name in self.ast.symdict
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obj = self.ast.symdict[node.expr.name]
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@ -1102,7 +1123,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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e = getattr(obj, node.attrname)
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self.write("%d'b%s" % (obj._nrbits, e._val))
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def visitIf(self, node):
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def visitIf(self, node, *args):
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first = True
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for test, suite in node.tests:
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if first:
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@ -1128,10 +1149,10 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.writeline()
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self.write("end")
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def visitKeyword(self, node):
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def visitKeyword(self, node, *args):
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self.visit(node.expr)
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def visitName(self, node):
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def visitName(self, node, *args):
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n = node.name
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if n == 'False':
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self.write("1'b0")
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@ -1139,6 +1160,8 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.write("1'b1")
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elif n in self.ast.vardict:
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self.write(n)
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elif n in self.ast.argnames:
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self.write(n)
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elif node.name in self.ast.symdict:
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obj = self.ast.symdict[n]
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if isinstance(obj, int):
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@ -1148,28 +1171,35 @@ class _ConvertVisitor(_ToVerilogMixin):
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else:
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self.write(n)
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else:
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raise AssertionError
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raise AssertionError("name ref: %s" % n)
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def visitPass(self, node):
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def visitPass(self, node, *args):
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self.write("// pass")
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def visitPrint(self, node):
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pass # XXX
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def visitPrintnl(self, node):
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pass # XXX
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def handlePrint(self, node):
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assert len(node.nodes) == 1
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s = node.nodes[0]
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self.write('$display(')
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self.visit(s, PRINT)
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self.write(');')
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def visitRaise(self, node):
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def visitPrint(self, node, *args):
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self.handlePrint(node)
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def visitPrintnl(self, node, *args):
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self.handlePrint(node)
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def visitRaise(self, node, *args):
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self.write('$display("Verilog: ')
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self.visit(node.expr1)
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self.write('");')
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self.writeline()
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self.write("$finish;")
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def visitReturn(self, node):
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def visitReturn(self, node, *args):
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self.write("disable %s;" % self.returnLabel)
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def visitSlice(self, node):
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def visitSlice(self, node, *args):
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if isinstance(node.expr, astNode.CallFunc) and \
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node.expr.node.obj is intbv:
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c = self.getVal(node)
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@ -1189,7 +1219,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.visit(node.upper)
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self.write("]")
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def visitStmt(self, node):
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def visitStmt(self, node, *args):
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for stmt in node.nodes:
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self.writeline()
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self.visit(stmt)
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@ -1197,22 +1227,26 @@ class _ConvertVisitor(_ToVerilogMixin):
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if isinstance(stmt, astNode.CallFunc) and hasattr(stmt, 'ast'):
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self.write(';')
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def visitSubscript(self, node):
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def visitSubscript(self, node, *args):
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self.visit(node.expr)
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self.write("[")
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assert len(node.subs) == 1
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self.visit(node.subs[0])
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self.write("]")
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def visitTuple(self, node):
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assert self.inYield
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def visitTuple(self, node, context=None, *args):
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assert context != None
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if context == PRINT:
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sep = ", "
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else:
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sep = " or "
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tpl = node.nodes
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self.visit(tpl[0])
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for elt in tpl[1:]:
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self.write(" or ")
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self.write(sep)
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self.visit(elt)
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def visitWhile(self, node):
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def visitWhile(self, node, *args):
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self.labelStack.append(node.breakLabel)
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self.labelStack.append(node.loopLabel)
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if node.breakLabel.isActive:
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@ -1234,12 +1268,10 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.labelStack.pop()
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self.labelStack.pop()
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def visitYield(self, node):
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self.inYield = True
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def visitYield(self, node, *args):
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self.write("@ (")
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self.visit(node.value)
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self.visit(node.value, YIELD)
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self.write(");")
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self.inYield = False
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class _ConvertAlwaysVisitor(_ConvertVisitor):
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@ -1248,14 +1280,12 @@ class _ConvertAlwaysVisitor(_ConvertVisitor):
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_ConvertVisitor.__init__(self, ast, blockBuf)
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self.funcBuf = funcBuf
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def visitFunction(self, node):
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def visitFunction(self, node, *args):
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w = node.code.nodes[-1]
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assert isinstance(w.body.nodes[0], astNode.Yield)
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sl = w.body.nodes[0].value
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self.inYield = True
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self.write("always @(")
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self.visit(sl)
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self.inYield = False
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self.visit(sl, YIELD)
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self.write(") begin: %s" % self.ast.name)
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self.indent()
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self.writeDeclarations()
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@ -1274,7 +1304,7 @@ class _ConvertInitialVisitor(_ConvertVisitor):
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_ConvertVisitor.__init__(self, ast, blockBuf)
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self.funcBuf = funcBuf
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def visitFunction(self, node):
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def visitFunction(self, node, *args):
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self.write("initial begin: %s" % self.ast.name)
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self.indent()
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self.writeDeclarations()
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@ -1302,7 +1332,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
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self.writeline()
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self.writeDeclaration(obj, name, "input")
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def visitFunction(self, node):
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def visitFunction(self, node, *args):
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self.write("function ")
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self.writeOutputDeclaration()
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self.indent()
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@ -1320,7 +1350,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
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self.write("endfunction")
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self.writeline(2)
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def visitReturn(self, node):
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def visitReturn(self, node, *args):
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self.write("%s = " % self.ast.name)
|
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self.visit(node.value)
|
||||
self.write(";")
|
||||
@ -1340,11 +1370,11 @@ class _ConvertTaskVisitor(_ConvertVisitor):
|
||||
output = name in self.ast.outputs
|
||||
input = name in self.ast.inputs
|
||||
inout = input and output
|
||||
dir = (inout and "inout") or (output and "output") or (input and "input")
|
||||
dir = (inout and "inout") or (output and "output") or "input"
|
||||
self.writeline()
|
||||
self.writeDeclaration(obj, name, dir)
|
||||
|
||||
def visitFunction(self, node):
|
||||
def visitFunction(self, node, *args):
|
||||
self.write("task %s;" % self.ast.name)
|
||||
self.indent()
|
||||
self.writeInterfaceDeclarations()
|
||||
|
||||
@ -139,20 +139,18 @@ class TestHec(unittest.TestCase):
|
||||
|
||||
return stimulus(), heccalc_inst, heccalc_v_inst
|
||||
|
||||
## def testPlain(self):
|
||||
## sim = self.bench(HecCalculatorPlain)
|
||||
## Simulation(sim).run()
|
||||
def testPlain(self):
|
||||
sim = self.bench(HecCalculatorPlain)
|
||||
Simulation(sim).run()
|
||||
|
||||
def testFunc(self):
|
||||
sim = self.bench(HecCalculatorFunc)
|
||||
Simulation(sim).run()
|
||||
|
||||
## def testTask(self):
|
||||
## sim = self.bench(HecCalculatorTask)
|
||||
## Simulation(sim).run()
|
||||
def testTask(self):
|
||||
sim = self.bench(HecCalculatorTask)
|
||||
Simulation(sim).run()
|
||||
|
||||
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
unittest.main()
|
||||
|
||||
@ -10,7 +10,7 @@ from myhdl import *
|
||||
|
||||
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
|
||||
|
||||
def inc(count, enable, clock, reset, n):
|
||||
def incRef(count, enable, clock, reset, n):
|
||||
""" Incrementer with enable.
|
||||
|
||||
count -- output
|
||||
@ -27,20 +27,66 @@ def inc(count, enable, clock, reset, n):
|
||||
if enable:
|
||||
count.next = (count + 1) % n
|
||||
|
||||
objfile = "inc_1.o"
|
||||
analyze_cmd = "iverilog -o %s inc_1.v tb_inc_1.v" % objfile
|
||||
## def incTaskFunc(count, count_in, enable, clock, reset, n):
|
||||
## if enable:
|
||||
## count.next = (count_in + 1) % n
|
||||
|
||||
## def incTask(count, enable, clock, reset, n):
|
||||
## while 1:
|
||||
## yield posedge(clock), negedge(reset)
|
||||
## if reset == ACTIVE_LOW:
|
||||
## count.next = 0
|
||||
## else:
|
||||
## incTaskFunc(count, count, enable, clock, reset, n)
|
||||
|
||||
def incTask(count, enable, clock, reset, n):
|
||||
|
||||
def incTaskFunc(cnt, enable, reset, n):
|
||||
if enable:
|
||||
cnt[:] = (cnt + 1) % n
|
||||
|
||||
def incTaskGen():
|
||||
cnt = intbv(0)[8:]
|
||||
while 1:
|
||||
yield posedge(clock), negedge(reset)
|
||||
if reset == ACTIVE_LOW:
|
||||
cnt[:] = 0
|
||||
count.next = 0
|
||||
else:
|
||||
# print count
|
||||
incTaskFunc(cnt, enable, reset, n)
|
||||
count.next = cnt
|
||||
|
||||
return incTaskGen()
|
||||
|
||||
|
||||
def incTaskFreeVar(count, enable, clock, reset, n):
|
||||
|
||||
def incTaskFunc():
|
||||
if enable:
|
||||
count.next = (count + 1) % n
|
||||
|
||||
def incTaskGen():
|
||||
while 1:
|
||||
yield posedge(clock), negedge(reset)
|
||||
if reset == ACTIVE_LOW:
|
||||
count.next = 0
|
||||
else:
|
||||
# print count
|
||||
incTaskFunc()
|
||||
|
||||
return incTaskGen()
|
||||
|
||||
|
||||
objfile = "inc_inst.o"
|
||||
analyze_cmd = "iverilog -o %s inc_inst.v tb_inc_inst.v" % objfile
|
||||
simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
|
||||
|
||||
|
||||
def top(count, enable, clock, reset, n, arch="myhdl"):
|
||||
if arch == "verilog":
|
||||
if path.exists(objfile):
|
||||
os.remove(objfile)
|
||||
os.system(analyze_cmd)
|
||||
return Cosimulation(simulate_cmd, **locals())
|
||||
else:
|
||||
inc_inst = inc(count, enable, clock, reset, n)
|
||||
return inc_inst
|
||||
def inc_v(count, enable, clock, reset):
|
||||
if path.exists(objfile):
|
||||
os.remove(objfile)
|
||||
os.system(analyze_cmd)
|
||||
return Cosimulation(simulate_cmd, **locals())
|
||||
|
||||
class TestInc(TestCase):
|
||||
|
||||
@ -50,6 +96,8 @@ class TestInc(TestCase):
|
||||
clock.next = not clock
|
||||
|
||||
def stimulus(self, enable, clock, reset):
|
||||
reset.next = INACTIVE_HIGH
|
||||
yield negedge(clock)
|
||||
reset.next = ACTIVE_LOW
|
||||
yield negedge(clock)
|
||||
reset.next = INACTIVE_HIGH
|
||||
@ -71,35 +119,44 @@ class TestInc(TestCase):
|
||||
if enable:
|
||||
expect = (expect + 1) % n
|
||||
yield delay(1)
|
||||
# print "%d count %s expect %s" % (now(), count, expect)
|
||||
# print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
|
||||
self.assertEqual(count, expect)
|
||||
self.assertEqual(count, count_v)
|
||||
|
||||
def bench(self):
|
||||
def bench(self, inc):
|
||||
|
||||
m = 8
|
||||
n = 2 ** m
|
||||
|
||||
count = Signal(intbv(0)[m:])
|
||||
count_v = Signal(intbv(0)[m:])
|
||||
enable, clock, reset = [Signal(bool()) for i in range(3)]
|
||||
enable = Signal(bool(0))
|
||||
clock, reset = [Signal(bool()) for i in range(2)]
|
||||
|
||||
inc_1 = toVerilog(top, count, enable, clock, reset, n=n)
|
||||
inc_v = top(count_v, enable, clock, reset, n=n, arch='verilog')
|
||||
inc_inst_ref = incRef(count, enable, clock, reset, n=n)
|
||||
inc_inst = toVerilog(inc, count, enable, clock, reset, n=n)
|
||||
inc_inst_v = inc_v(count_v, enable, clock, reset)
|
||||
clk_1 = self.clockGen(clock)
|
||||
st_1 = self.stimulus(enable, clock, reset)
|
||||
ch_1 = self.check(count, count_v, enable, clock, reset, n=n)
|
||||
|
||||
sim = Simulation(inc_1, inc_v, clk_1, st_1, ch_1)
|
||||
sim = Simulation(inc_inst_ref, inc_inst_v, clk_1, st_1, ch_1)
|
||||
return sim
|
||||
|
||||
def test(self):
|
||||
def testIncRef(self):
|
||||
""" Check increment operation """
|
||||
sim = self.bench()
|
||||
sim = self.bench(incRef)
|
||||
sim.run(quiet=1)
|
||||
|
||||
def testIncTask(self):
|
||||
sim = self.bench(incTask)
|
||||
sim.run(quiet=1)
|
||||
|
||||
def testIncTaskFreeVar(self):
|
||||
sim = self.bench(incTaskFreeVar)
|
||||
sim.run(quiet=1)
|
||||
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
unittest.main()
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user