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print ast

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jand 2004-02-03 14:40:10 +00:00
parent f800e21adc
commit f4ed9c5399
1 changed files with 1 additions and 1 deletions
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myhdl/_toVerilog/_analyze.py
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@ -108,7 +108,7 @@ def _analyzeGens(top, genNames):
s = inspect.getsource(f)
s = s.lstrip()
ast = compiler.parse(s)
print ast
# print ast
ast.sourcefile = inspect.getsourcefile(f)
ast.lineoffset = inspect.getsourcelines(f)[1]-1
ast.symdict = f.f_globals.copy()