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tristate rename
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@ -130,7 +130,7 @@ from myhdl import conversion
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from conversion import toVerilog
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from conversion import toVHDL
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from _tristate import TristateBus
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from _tristate import Tristate
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__all__ = ["bin",
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@ -158,7 +158,7 @@ __all__ = ["bin",
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"toVerilog",
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"toVHDL",
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"conversion",
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"TristateBus"
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"Tristate"
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]
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@ -8,20 +8,20 @@ class BusContentionWarning(UserWarning):
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warnings.filterwarnings('always', r".*", BusContentionWarning)
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class TristateBus(Signal):
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class Tristate(Signal):
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def __new__(cls, val, delay=None):
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""" Return a new TristateBus (default or delay 0) or DelayedTristateBus """
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if delay is not None:
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if delay < 0:
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raise TypeError("Signal: delay should be >= 0")
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return object.__new__(DelayedTristateBus)
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return object.__new__(DelayedTristate)
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else:
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return object.__new__(cls)
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def __init__(self, val):
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self._drivers = []
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super(TristateBus, self).__init__(val)
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super(Tristate, self).__init__(val)
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self._val = None
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def driver(self):
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@ -42,7 +42,7 @@ class TristateBus(Signal):
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def _update(self):
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self._resolve()
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return super(TristateBus, self)._update()
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return super(Tristate, self)._update()
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class _TristateDriver(Signal):
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@ -63,13 +63,13 @@ class _TristateDriver(Signal):
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next = property(Signal._get_next, _set_next, None, "'next' access methods")
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class DelayedTristateBus(DelayedSignal, TristateBus):
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class DelayedTristate(DelayedSignal, Tristate):
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def __init__(self, val, delay=1):
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self._drivers = []
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super(DelayedTristateBus, self).__init__(val, delay)
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super(DelayedTristate, self).__init__(val, delay)
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self._val = None
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def _update(self):
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self._resolve()
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return super(DelayedTristateBus, self)._update()
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return super(DelayedTristate, self)._update()
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@ -27,7 +27,7 @@ def PrintBench():
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yield delay(10)
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#print "i1 is %s" % i1
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yield delay(10)
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print "%% %s" % i1
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# print "%% %s" % i1
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return logic
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