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Changed the clock source to actually have the initial value outputted for a while.

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Henry Gomersall 2016-02-26 23:03:06 +00:00
parent 843eb9eb4a
commit f5ce6fb533
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GPG Key ID: 67F4313D73CED5A6
1 changed files with 1 additions and 3 deletions
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myhdl/test/conversion/general/test_initial_values.py
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@ -31,8 +31,6 @@ def initial_value_bench(initial_val, change_input_signal):
@instance @instance
def clkgen(): def clkgen():
clk.next = 1
for n in range(N): for n in range(N):
yield delay(10) yield delay(10)
clk.next = not clk clk.next = not clk
@ -43,7 +41,7 @@ def initial_value_bench(initial_val, change_input_signal):
def output_driver(): def output_driver():
output_signal.next = input_signal output_signal.next = input_signal
@always(clk) @always(clk.posedge)
def compare_output(): def compare_output():
input_signal.next = update_val input_signal.next = update_val