diff --git a/myhdl/_toVHDL/_convert.py b/myhdl/_toVHDL/_convert.py
index a5cbb0cb..b2af84e6 100644
--- a/myhdl/_toVHDL/_convert.py
+++ b/myhdl/_toVHDL/_convert.py
@@ -394,8 +394,6 @@ class _ConvertVisitor(_ToVerilogMixin):
         self.binaryOp(node, '+')
     def visitFloorDiv(self, node, *args):
         self.binaryOp(node, '/')
-    def visitLeftShift(self, node, *args):
-        self.binaryOp(node, '<<')
     def visitMod(self, node, context=None, *args):
         if context == _context.PRINT:
             self.visit(node.left, _context.PRINT)
@@ -409,13 +407,22 @@ class _ConvertVisitor(_ToVerilogMixin):
          self.binaryOp(node, '**')
     def visitSub(self, node, *args):
         self.binaryOp(node, "-")
-    def visitRightShift(self, node, *args):
-        # self.binaryOp(node, '<<')
-        self.write("shift_right(")
+
+
+    def shiftOp(self, node, op=None):
+        if isinstance(node.vhdlObj, vhdl_int):
+            self.write("to_integer(")
+        self.write("%s(" % op)
         self.visit(node.left)
         self.write(", ")
         self.visit(node.right)
+        if isinstance(node.vhdlObj, vhdl_int):
+            self.write(")")
         self.write(")")
+    def visitLeftShift(self, node, *args):
+        self.shiftOp(node, "shift_left")
+    def visitRightShift(self, node, *args):
+        self.shiftOp(node, "shift_right")
 
     def checkOpWithNegIntbv(self, node, op):
         if op in ("+", "-", "*", "&&", "||", "!"):
@@ -527,7 +534,7 @@ class _ConvertVisitor(_ToVerilogMixin):
         convOpen, convClose = "", ""
         if isinstance(lhs.vhdlObj, vhdl_unsigned):
             if isinstance(rhs.vhdlObj, vhdl_unsigned) and \
-                   (lhs.vhdlObj.size == rhs.vhdlObj.size):
+               (lhs.vhdlObj.size == rhs.vhdlObj.size):
                 pass
             else:
                 convOpen, convClose = "to_unsigned(", ", %s)" % lhs.vhdlObj.size
@@ -1484,6 +1491,10 @@ class _AnnotateTypesVisitor(_ToVerilogMixin):
         self.visit(node.right)
         r = node.right.vhdlObj
         l = node.left.vhdlObj
+        if op in ('+', '-', '%'):
+            s = max(l.size, r.size)
+        elif op in ('*',):
+            s = l.size + r.size
         if isinstance(r, vhdl_int) and isinstance(l, vhdl_int):
             node.vhdlObj = vhdl_int()
         elif isinstance(r, (vhdl_signed, vhdl_int)) and isinstance(l, (vhdl_signed, vhdl_int)):
@@ -1492,8 +1503,16 @@ class _AnnotateTypesVisitor(_ToVerilogMixin):
             node.vhdlObj = vhdl_unsigned(max(l.size, r.size))
         else:
             node.vhdlObj = vhdl_int()
-            
-    visitAdd = visitSub = visitMod = binaryOp
+
+    def visitAdd(self, node):
+        self.binaryOp(node, op='+')
+    def visitSub(self, node):
+        self.binaryOp(node, op='-')
+    def visitMod(self, node):
+        self.binaryOp(node, op='%')
+    def visitMul(self, node):
+        self.binaryOp(node, op='+')
+
     
     def multiBitOp(self, node):
         self.visitChildNodes(node)
diff --git a/myhdl/test/toVHDL/test_ops.py b/myhdl/test/toVHDL/test_ops.py
index 739f29cd..2d968b11 100644
--- a/myhdl/test/toVHDL/test_ops.py
+++ b/myhdl/test/toVHDL/test_ops.py
@@ -35,16 +35,16 @@ def binaryOps(
 ##         Bitxor.next = left ^ right
 ##         if right != 0:
 ##             FloorDiv.next = left // right
-##         if left < 256 and right < 40:
-##             LeftShift.next = left << right
+        if left < 256 and right < 40:
+            LeftShift.next = left << right
 ##         if right != 0:
 ##             Modulo.next = left % right
-##         Mul.next = left * right
+        Mul.next = left * right
         # Icarus doesn't support ** yet
         #if left < 256 and right < 40:
         #    Pow.next = left ** right
 ##         Pow.next = 0
-##         RightShift.next = left >> right
+        RightShift.next = left >> right
         if left >= right:
             Sub.next = left - right
         Sum.next = left + right
@@ -137,37 +137,33 @@ def binaryBench(m, n):
 ##             self.assertEqual(Bitor, Bitor_v)
 ##             self.assertEqual(Bitxor, Bitxor_v)
 ##             self.assertEqual(FloorDiv, FloorDiv_v)
-##             self.assertEqual(LeftShift, LeftShift_v)
+            
+##             print LeftShift
+
+
 ##             self.assertEqual(Modulo, Modulo_v)
-##             self.assertEqual(Mul, Mul_v)
 ##             # self.assertEqual(Pow, Pow_v)
-##             self.assertEqual(RightShift, RightShift_v)
-##             self.assertEqual(Sub, Sub_v)
-##             self.assertEqual(Sum, Sum_v)
+
+            
+##             print RightShift
+##             print Mul
             print Sub
             print Sum
-            print int(EQ)
-            print int(NE)
-            print int(LT)
-            print int(GT)
-            print int(LE)
-            print int(GE)
-            print int(Booland)
-            print int(Boolor)
-##             self.assertEqual(EQ, EQ_v)
-##             self.assertEqual(NE, NE_v)
-##             self.assertEqual(LT, LT_v)
-##             self.assertEqual(GT, GT_v)
-##             self.assertEqual(LE, LE_v)
-##             self.assertEqual(GE, GE_v)
-##             self.assertEqual(Booland, Booland_v)
-##             self.assertEqual(Boolor, Boolor_v)
+##             print int(EQ)
+##             print int(NE)
+##             print int(LT)
+##             print int(GT)
+##             print int(LE)
+##             print int(GE)
+##             print int(Booland)
+##             print int(Boolor)
 
     return binops, stimulus(), check()
 
 
 def testBinary():
-    for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
+    # for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
+    for m, n in ((4, 4,),):
         yield checkBinary, m, n
 
 def checkBinary(m, n):