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jand 2006-09-10 20:20:17 +00:00
parent 48c63e0a09
commit f719e27bf7
2 changed files with 49 additions and 34 deletions
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33
myhdl/_toVHDL/_convert.py
View File

@ -394,8 +394,6 @@ class _ConvertVisitor(_ToVerilogMixin):
self.binaryOp(node, '+') self.binaryOp(node, '+')
def visitFloorDiv(self, node, *args): def visitFloorDiv(self, node, *args):
self.binaryOp(node, '/') self.binaryOp(node, '/')
def visitLeftShift(self, node, *args):
self.binaryOp(node, '<<')
def visitMod(self, node, context=None, *args): def visitMod(self, node, context=None, *args):
if context == _context.PRINT: if context == _context.PRINT:
self.visit(node.left, _context.PRINT) self.visit(node.left, _context.PRINT)
@ -409,13 +407,22 @@ class _ConvertVisitor(_ToVerilogMixin):
self.binaryOp(node, '**') self.binaryOp(node, '**')
def visitSub(self, node, *args): def visitSub(self, node, *args):
self.binaryOp(node, "-") self.binaryOp(node, "-")
def visitRightShift(self, node, *args):
# self.binaryOp(node, '<<')
self.write("shift_right(") def shiftOp(self, node, op=None):
if isinstance(node.vhdlObj, vhdl_int):
self.write("to_integer(")
self.write("%s(" % op)
self.visit(node.left) self.visit(node.left)
self.write(", ") self.write(", ")
self.visit(node.right) self.visit(node.right)
if isinstance(node.vhdlObj, vhdl_int):
self.write(")")
self.write(")") self.write(")")
def visitLeftShift(self, node, *args):
self.shiftOp(node, "shift_left")
def visitRightShift(self, node, *args):
self.shiftOp(node, "shift_right")
def checkOpWithNegIntbv(self, node, op): def checkOpWithNegIntbv(self, node, op):
if op in ("+", "-", "*", "&&", "||", "!"): if op in ("+", "-", "*", "&&", "||", "!"):
@ -527,7 +534,7 @@ class _ConvertVisitor(_ToVerilogMixin):
convOpen, convClose = "", "" convOpen, convClose = "", ""
if isinstance(lhs.vhdlObj, vhdl_unsigned): if isinstance(lhs.vhdlObj, vhdl_unsigned):
if isinstance(rhs.vhdlObj, vhdl_unsigned) and \ if isinstance(rhs.vhdlObj, vhdl_unsigned) and \
(lhs.vhdlObj.size == rhs.vhdlObj.size): (lhs.vhdlObj.size == rhs.vhdlObj.size):
pass pass
else: else:
convOpen, convClose = "to_unsigned(", ", %s)" % lhs.vhdlObj.size convOpen, convClose = "to_unsigned(", ", %s)" % lhs.vhdlObj.size
@ -1484,6 +1491,10 @@ class _AnnotateTypesVisitor(_ToVerilogMixin):
self.visit(node.right) self.visit(node.right)
r = node.right.vhdlObj r = node.right.vhdlObj
l = node.left.vhdlObj l = node.left.vhdlObj
if op in ('+', '-', '%'):
s = max(l.size, r.size)
elif op in ('*',):
s = l.size + r.size
if isinstance(r, vhdl_int) and isinstance(l, vhdl_int): if isinstance(r, vhdl_int) and isinstance(l, vhdl_int):
node.vhdlObj = vhdl_int() node.vhdlObj = vhdl_int()
elif isinstance(r, (vhdl_signed, vhdl_int)) and isinstance(l, (vhdl_signed, vhdl_int)): elif isinstance(r, (vhdl_signed, vhdl_int)) and isinstance(l, (vhdl_signed, vhdl_int)):
@ -1493,7 +1504,15 @@ class _AnnotateTypesVisitor(_ToVerilogMixin):
else: else:
node.vhdlObj = vhdl_int() node.vhdlObj = vhdl_int()
visitAdd = visitSub = visitMod = binaryOp def visitAdd(self, node):
self.binaryOp(node, op='+')
def visitSub(self, node):
self.binaryOp(node, op='-')
def visitMod(self, node):
self.binaryOp(node, op='%')
def visitMul(self, node):
self.binaryOp(node, op='+')
def multiBitOp(self, node): def multiBitOp(self, node):
self.visitChildNodes(node) self.visitChildNodes(node)

48
myhdl/test/toVHDL/test_ops.py
View File

@ -35,16 +35,16 @@ def binaryOps(
## Bitxor.next = left ^ right ## Bitxor.next = left ^ right
## if right != 0: ## if right != 0:
## FloorDiv.next = left // right ## FloorDiv.next = left // right
## if left < 256 and right < 40: if left < 256 and right < 40:
## LeftShift.next = left << right LeftShift.next = left << right
## if right != 0: ## if right != 0:
## Modulo.next = left % right ## Modulo.next = left % right
## Mul.next = left * right Mul.next = left * right
# Icarus doesn't support ** yet # Icarus doesn't support ** yet
#if left < 256 and right < 40: #if left < 256 and right < 40:
# Pow.next = left ** right # Pow.next = left ** right
## Pow.next = 0 ## Pow.next = 0
## RightShift.next = left >> right RightShift.next = left >> right
if left >= right: if left >= right:
Sub.next = left - right Sub.next = left - right
Sum.next = left + right Sum.next = left + right
@ -137,37 +137,33 @@ def binaryBench(m, n):
## self.assertEqual(Bitor, Bitor_v) ## self.assertEqual(Bitor, Bitor_v)
## self.assertEqual(Bitxor, Bitxor_v) ## self.assertEqual(Bitxor, Bitxor_v)
## self.assertEqual(FloorDiv, FloorDiv_v) ## self.assertEqual(FloorDiv, FloorDiv_v)
## self.assertEqual(LeftShift, LeftShift_v)
## print LeftShift
## self.assertEqual(Modulo, Modulo_v) ## self.assertEqual(Modulo, Modulo_v)
## self.assertEqual(Mul, Mul_v)
## # self.assertEqual(Pow, Pow_v) ## # self.assertEqual(Pow, Pow_v)
## self.assertEqual(RightShift, RightShift_v)
## self.assertEqual(Sub, Sub_v)
## self.assertEqual(Sum, Sum_v) ## print RightShift
## print Mul
print Sub print Sub
print Sum print Sum
print int(EQ) ## print int(EQ)
print int(NE) ## print int(NE)
print int(LT) ## print int(LT)
print int(GT) ## print int(GT)
print int(LE) ## print int(LE)
print int(GE) ## print int(GE)
print int(Booland) ## print int(Booland)
print int(Boolor) ## print int(Boolor)
## self.assertEqual(EQ, EQ_v)
## self.assertEqual(NE, NE_v)
## self.assertEqual(LT, LT_v)
## self.assertEqual(GT, GT_v)
## self.assertEqual(LE, LE_v)
## self.assertEqual(GE, GE_v)
## self.assertEqual(Booland, Booland_v)
## self.assertEqual(Boolor, Boolor_v)
return binops, stimulus(), check() return binops, stimulus(), check()
def testBinary(): def testBinary():
for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): # for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
for m, n in ((4, 4,),):
yield checkBinary, m, n yield checkBinary, m, n
def checkBinary(m, n): def checkBinary(m, n):