diff --git a/myhdl/_toVerilog/_analyze.py b/myhdl/_toVerilog/_analyze.py
index 13fd738e..1423d211 100644
--- a/myhdl/_toVerilog/_analyze.py
+++ b/myhdl/_toVerilog/_analyze.py
@@ -211,6 +211,13 @@ class _NotSupportedVisitor(_ToVerilogMixin):
             self.visit(suite, _context.UNKNOWN)
         if node.else_:
             self.visit(node.else_, _context.UNKNOWN)
+        
+    def visitPrintnl(self, node, *args):
+        if node.dest is not None:
+            self.raiseError(node, _error.NotSupported, "printing to a file with >> syntax")
+        self.visitChildNodes(node, *args)
+        
+    visitPrint = visitPrintnl
 
 
 def getNrBits(obj):
diff --git a/myhdl/test/toVerilog/test_errors.py b/myhdl/test/toVerilog/test_errors.py
index 184d004b..4e4a0365 100644
--- a/myhdl/test/toVerilog/test_errors.py
+++ b/myhdl/test/toVerilog/test_errors.py
@@ -145,6 +145,29 @@ def taskReturnVal(count, enable, clock, reset, n):
                 h2(cnt)
                 count.next = count + 1
 
+
+def printnlToFile(count, enable, clock, reset, n):
+    cnt = intbv()[8:]
+    while 1:
+        yield posedge(clock), negedge(reset)
+        if reset == ACTIVE_LOW:
+            count.next = 0
+        else:
+            if enable:
+                print >> f, count
+                count.next = count + 1
+
+def printToFile(count, enable, clock, reset, n):
+    cnt = intbv()[8:]
+    while 1:
+        yield posedge(clock), negedge(reset)
+        if reset == ACTIVE_LOW:
+            count.next = 0
+        else:
+            if enable:
+                print >> f, count,
+                count.next = count + 1
+
        
 
 objfile = "inc_inst.o"
@@ -291,7 +314,21 @@ class TestErr(TestCase):
         else:
             self.fail()
 
-            
+    def testPrintnlToFile(self):
+        try:
+            self.bench(printnlToFile)
+        except ToVerilogError, e:
+            self.assertEqual(e.kind, _error.NotSupported)
+        else:
+            self.fail()
+
+    def testPrintToFile(self):
+        try:
+            self.bench(printToFile)
+        except ToVerilogError, e:
+            self.assertEqual(e.kind, _error.NotSupported)
+        else:
+            self.fail()
 
 
 if __name__ == '__main__':