Added tests, code and docs to implement directory setting for toVHDL and toVerilog.

--HG--
branch : 0.9-dev-set_file_dir

doc/source/manual/reference.rst

@@ -710,6 +710,11 @@ Conversion
        This attribute is used to overwrite the default top-level instance name and the
        basename of the Verilog output filename.
 
+    .. attribute:: directory
+
+       This attribute is used to set the directory to which converted verilog
+       files are written. By default, the current working directory is used.
+
     .. attribute:: timescale
 
        This attribute is used to set the timescale in Verilog format. The assigned value
@@ -735,6 +740,11 @@ Conversion
        This attribute is used to overwrite the default top-level
        instance name and the basename of the VHDL output.
 
+    .. attribute:: directory
+
+       This attribute is used to set the directory to which converted VHDL
+       files are written. By default, the current working directory is used.
+
     .. attribute:: component_declarations
 
        This attribute can be used to add component declarations to the

myhdl/conversion/_toVHDL.py

@@ -24,6 +24,7 @@
 
 import sys
 import math
+import os
 
 import inspect
 from datetime import datetime
@@ -86,6 +87,7 @@ def _makeDoc(doc, indent=''):
 class _ToVHDLConvertor(object):
 
     __slots__ = ("name",
+                 "directory",                 
                  "component_declarations",
                  "header",
                  "no_myhdl_header",
@@ -98,6 +100,7 @@ class _ToVHDLConvertor(object):
 
     def __init__(self):
         self.name = None
+        self.directory = None        
         self.component_declarations = None
         self.header = ''
         self.no_myhdl_header = False
@@ -130,10 +133,15 @@ class _ToVHDLConvertor(object):
         finally:
             _converting = 0
 
+        if self.directory is None:
+            directory = ''
+        else:
+            directory = self.directory
+
         compDecls = self.component_declarations
         useClauses = self.use_clauses
 
-        vpath = name + ".vhd"
+        vpath = os.path.join(directory, name + ".vhd")
         vfile = open(vpath, 'w')
         ppath = "pck_myhdl_%s.vhd" % _shortversion
         pfile = None

myhdl/conversion/_toVerilog.py

@@ -24,6 +24,8 @@
 
 import sys
 import math
+import os
+
 import inspect
 from datetime import datetime
 import ast
@@ -80,6 +82,7 @@ def _makeDoc(doc, indent=''):
 class _ToVerilogConvertor(object):
 
     __slots__ = ("name",
+                 "directory",
                  "timescale",
                  "standard",
                  "prefer_blocking_assignments",
@@ -93,6 +96,7 @@ class _ToVerilogConvertor(object):
 
     def __init__(self):
         self.name = None
+        self.directory = None
         self.timescale = "1ns/10ps"
         self.standard = '2001'
         self.prefer_blocking_assignments = True
@@ -125,7 +129,13 @@ class _ToVerilogConvertor(object):
         finally:
             _converting = 0
 
-        vpath = name + ".v"
+        if self.directory is None:
+            directory = ''
+        else:
+            directory = self.directory
+
+        vfilename = name + ".v"
+        vpath = os.path.join(directory, vfilename)
         vfile = open(vpath, 'w')
 
         ### initialize properly ###
@@ -154,7 +164,7 @@ class _ToVerilogConvertor(object):
 
         # don't write testbench if module has no ports
         if len(intf.argnames) > 0 and not toVerilog.no_testbench:
-            tbpath = "tb_" + vpath
+            tbpath = os.path.join(directory, "tb_" + vfilename)
             tbfile = open(tbpath, 'w')
             _writeTestBench(tbfile, intf, self.trace)
             tbfile.close()

myhdl/test/conversion/general/test_set_dir.py

@@ -0,0 +1,73 @@
+import os
+
+from myhdl import *
+from tempfile import mkdtemp
+from shutil import rmtree
+
+def simple_dir_model(din, dout, clk):
+    """ Simple convertible model """
+
+    @always(clk.posedge)
+    def register():
+            dout.next = din
+
+    return register
+        
+
+def test_toVHDL_set_dir():
+    
+    tmp_dir = mkdtemp()
+
+    din = Signal(intbv(0)[5:])
+    dout = Signal(intbv(0)[5:])
+    clock = Signal(bool(0))
+
+    try:
+        toVHDL.directory = tmp_dir
+        toVHDL(simple_dir_model, din, dout, clock)
+
+        assert os.path.exists(os.path.join(tmp_dir, 'simple_dir_model.vhd'))
+
+    finally:
+        toVHDL.directory = None        
+        rmtree(tmp_dir)
+
+
+def test_toVerilog_set_dir():
+    
+    tmp_dir = mkdtemp()
+
+    din = Signal(intbv(0)[5:])
+    dout = Signal(intbv(0)[5:])
+    clock = Signal(bool(0))
+    toVerilog.no_testbench = True
+
+    try:
+        toVerilog.directory = tmp_dir
+        toVerilog(simple_dir_model, din, dout, clock)
+
+        assert os.path.exists(os.path.join(tmp_dir, 'simple_dir_model.v'))
+
+    finally:
+        toVerilog.directory = None
+        rmtree(tmp_dir)
+
+def test_toVerilog_testbench_set_dir():
+    
+    tmp_dir = mkdtemp()
+
+    din = Signal(intbv(0)[5:])
+    dout = Signal(intbv(0)[5:])
+    clock = Signal(bool(0))
+
+    toVerilog.no_testbench = False
+
+    try:
+        toVerilog.directory = tmp_dir
+        toVerilog(simple_dir_model, din, dout, clock)
+
+        assert os.path.exists(os.path.join(tmp_dir, 'tb_simple_dir_model.v'))
+
+    finally:
+        toVerilog.directory = None        
+        rmtree(tmp_dir)