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added an interface with constant test
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@ -22,21 +22,43 @@ class ZBus:
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self.z = Signal(intbv(0, min=z.min, max=z.max))
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class Intf3:
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def __init__(self,z ):
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def __init__(self, z):
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self.z = ZBus(z)
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class IntfWithConstant1:
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def __init__(self):
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self.const1 = 707
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self.const2 = 3
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class IntfWithConstant2:
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def __init__(self):
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self.a = 9
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self.b = 10
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self.c = 1729
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self.more_constants = IntfWithConstant1()
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def m_assign(y, x):
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@always_comb
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def assign():
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y.next = x
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return assign
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def m_top_assign(x,y,z):
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"""
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This module does not test top-level interfaces,
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it only tests intermediate interfaces.
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"""
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i1,i2 = Intf1(x), Intf2(y)
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x.assign(i1.x)
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i2.y.assign(y)
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gm = m_assign_comb(i1, i2)
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return gm
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def m_assign_comb(x, y):
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ga1 = m_assign(x, i1.x) # x = i1.x
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ga2 = m_assign(i2.y, y) # i2.y = y
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gm1 = m_assign_intf(i1, i2)
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return ga1, ga2, gm1
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def m_assign_intf(x, y):
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@always_comb
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def rtl():
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x.x.next = y.y
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@ -89,10 +111,58 @@ def c_testbench_two():
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return tb_dut, tb_stim
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def m_top_const(clock, reset, x, y, intf):
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@always_seq(clock.posedge, reset=reset)
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def rtl1():
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v = intf.a**3 + intf.b**3
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x.next = v - intf.c
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@always_comb
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def rtl2():
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y.next = x + intf.more_constants.const1 - \
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intf.more_constants.const2*235 - 2
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return rtl1, rtl2
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def c_testbench_three():
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"""
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this will test the use of constants in an inteface
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as well as top-level interface conversion.
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"""
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clock = Signal(bool(0))
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reset = ResetSignal(0, active=0, async=True)
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x = Signal(intbv(3, min=-5000, max=5000))
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y = Signal(intbv(4, min=-200, max=200))
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intf = IntfWithConstant2()
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tbdut = m_top_const(clock, reset, x, y, intf)
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@instance
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def tbclk():
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while True:
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yield delay(3)
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clock.next = not clock
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@instance
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def tbstim():
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reset.next = reset.active
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yield delay(33)
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reset.next = not reset.active
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yield clock.posedge
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yield clock.posedge
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print("x: %d" % (x,))
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print("y: %d" % (y,))
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assert x == 0
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assert y == 0
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raise StopSimulation
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return tbdut, tbclk, tbstim
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def test_one_analyze():
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x,y,z = [Signal(intbv(0, min=-8, max=8))
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for _ in range(3)]
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analyze(m_top_assign,x,y,z)
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analyze(m_top_assign, x, y, z)
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def test_one_verify():
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assert verify(c_testbench_one) == 0
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@ -100,17 +170,36 @@ def test_one_verify():
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def test_two_analyze():
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x,y,z = [Signal(intbv(0, min=-8, max=8))
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for _ in range(3)]
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analyze(m_top_multi_comb,x,y,z)
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analyze(m_top_multi_comb, x, y, z)
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def test_two_verify():
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assert verify(c_testbench_two) == 0
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def test_three_analyze():
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clock = Signal(bool(0))
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reset = ResetSignal(0, active=0, async=True)
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x = Signal(intbv(3, min=-5000, max=5000))
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y = Signal(intbv(4, min=-200, max=200))
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intf = IntfWithConstant2()
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analyze(m_top_const, clock, reset, x, y, const)
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def test_three_verify():
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assert verify(c_testbench_three) == 0
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if __name__ == '__main__':
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print(sys.argv[1])
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verify.simulator = analyze.simulator = sys.argv[1]
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print("*** verify myhdl simulation")
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Simulation(c_testbench_one()).run()
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Simulation(c_testbench_two()).run()
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#Simulation(c_testbench_one()).run()
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#Simulation(c_testbench_two()).run()
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Simulation(c_testbench_three()).run()
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print("*** myhdl simulation ok")
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print(verify(c_testbench_one))
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print(verify(c_testbench_two))
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print("")
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print("*** myhdl verify conversion")
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#print(verify(c_testbench_one))
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#print(verify(c_testbench_two))
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print(verify(c_testbench_three))
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print("*** myhdl conversion ok")
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print("")
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