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mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00

added an interface with constant test

This commit is contained in:
Christopher Felton 2015-03-18 09:24:00 -05:00
parent 4349b6169c
commit f921260dd0

View File

@ -22,21 +22,43 @@ class ZBus:
self.z = Signal(intbv(0, min=z.min, max=z.max))
class Intf3:
def __init__(self,z ):
def __init__(self, z):
self.z = ZBus(z)
class IntfWithConstant1:
def __init__(self):
self.const1 = 707
self.const2 = 3
class IntfWithConstant2:
def __init__(self):
self.a = 9
self.b = 10
self.c = 1729
self.more_constants = IntfWithConstant1()
def m_assign(y, x):
@always_comb
def assign():
y.next = x
return assign
def m_top_assign(x,y,z):
"""
This module does not test top-level interfaces,
it only tests intermediate interfaces.
"""
i1,i2 = Intf1(x), Intf2(y)
x.assign(i1.x)
i2.y.assign(y)
gm = m_assign_comb(i1, i2)
return gm
def m_assign_comb(x, y):
ga1 = m_assign(x, i1.x) # x = i1.x
ga2 = m_assign(i2.y, y) # i2.y = y
gm1 = m_assign_intf(i1, i2)
return ga1, ga2, gm1
def m_assign_intf(x, y):
@always_comb
def rtl():
x.x.next = y.y
@ -89,10 +111,58 @@ def c_testbench_two():
return tb_dut, tb_stim
def m_top_const(clock, reset, x, y, intf):
@always_seq(clock.posedge, reset=reset)
def rtl1():
v = intf.a**3 + intf.b**3
x.next = v - intf.c
@always_comb
def rtl2():
y.next = x + intf.more_constants.const1 - \
intf.more_constants.const2*235 - 2
return rtl1, rtl2
def c_testbench_three():
"""
this will test the use of constants in an inteface
as well as top-level interface conversion.
"""
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
x = Signal(intbv(3, min=-5000, max=5000))
y = Signal(intbv(4, min=-200, max=200))
intf = IntfWithConstant2()
tbdut = m_top_const(clock, reset, x, y, intf)
@instance
def tbclk():
while True:
yield delay(3)
clock.next = not clock
@instance
def tbstim():
reset.next = reset.active
yield delay(33)
reset.next = not reset.active
yield clock.posedge
yield clock.posedge
print("x: %d" % (x,))
print("y: %d" % (y,))
assert x == 0
assert y == 0
raise StopSimulation
return tbdut, tbclk, tbstim
def test_one_analyze():
x,y,z = [Signal(intbv(0, min=-8, max=8))
for _ in range(3)]
analyze(m_top_assign,x,y,z)
analyze(m_top_assign, x, y, z)
def test_one_verify():
assert verify(c_testbench_one) == 0
@ -100,17 +170,36 @@ def test_one_verify():
def test_two_analyze():
x,y,z = [Signal(intbv(0, min=-8, max=8))
for _ in range(3)]
analyze(m_top_multi_comb,x,y,z)
analyze(m_top_multi_comb, x, y, z)
def test_two_verify():
assert verify(c_testbench_two) == 0
def test_three_analyze():
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
x = Signal(intbv(3, min=-5000, max=5000))
y = Signal(intbv(4, min=-200, max=200))
intf = IntfWithConstant2()
analyze(m_top_const, clock, reset, x, y, const)
def test_three_verify():
assert verify(c_testbench_three) == 0
if __name__ == '__main__':
print(sys.argv[1])
verify.simulator = analyze.simulator = sys.argv[1]
print("*** verify myhdl simulation")
Simulation(c_testbench_one()).run()
Simulation(c_testbench_two()).run()
#Simulation(c_testbench_one()).run()
#Simulation(c_testbench_two()).run()
Simulation(c_testbench_three()).run()
print("*** myhdl simulation ok")
print(verify(c_testbench_one))
print(verify(c_testbench_two))
print("")
print("*** myhdl verify conversion")
#print(verify(c_testbench_one))
#print(verify(c_testbench_two))
print(verify(c_testbench_three))
print("*** myhdl conversion ok")
print("")