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Merge pull request #137 from nturley/master
fix bug in test_custom tests
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commit
fb70bb2fc4
@ -74,10 +74,10 @@ def inc(count, enable, clock, reset, n):
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__vhdl__ = \
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"""
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process (%(clock)s, %(reset)s) begin
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if (reset = '0') then
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if (%(reset)s = '0') then
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%(count)s <= (others => '0');
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elsif rising_edge(%(clock)s) then
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if (enable = '1') then
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if (%(enable)s = '1') then
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%(count)s <= (%(count)s + 1) mod %(n)s;
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end if;
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end if;
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@ -104,11 +104,11 @@ def incErr(count, enable, clock, reset, n):
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__vhdl__ = \
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"""
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always @(posedge %(clock)s, negedge %(reset)s) begin
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if (reset == 0) begin
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if (%(reset)s == 0) begin
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%(count)s <= 0;
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end
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else begin
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if (enable) begin
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if (%(enable)s) begin
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%(count)s <= (%(countq)s + 1) %% %(n)s;
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end
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end
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@ -151,10 +151,10 @@ def inc_seq(count, nextCount, enable, clock, reset):
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__vhdl__ = \
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"""
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process (%(clock)s, %(reset)s) begin
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if (reset = '0') then
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if (%(reset)s = '0') then
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%(count)s <= (others => '0');
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elsif rising_edge(%(clock)s) then
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if (enable = '1') then
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if (%(enable)s = '1') then
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%(count)s <= %(nextCount)s;
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end if;
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end if;
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@ -74,10 +74,10 @@ def inc(count, enable, clock, reset, n):
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inc.vhdl_code = \
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"""
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process ($clock, $reset) begin
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if (reset = '0') then
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if ($reset = '0') then
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$count <= (others => '0');
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elsif rising_edge($clock) then
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if (enable = '1') then
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if ($enable = '1') then
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$count <= ($count + 1) mod $n;
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end if;
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end if;
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@ -104,11 +104,11 @@ def incErr(count, enable, clock, reset, n):
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incErr.vhdl_code = \
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"""
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always @(posedge $clock, negedge $reset) begin
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if (reset == 0) begin
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if ($reset == 0) begin
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$count <= 0;
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end
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else begin
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if (enable) begin
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if ($enable) begin
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$count <= ($countq + 1) %% $n;
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end
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end
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@ -151,10 +151,10 @@ def inc_seq(count, nextCount, enable, clock, reset):
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inc_seq.vhdl_code = \
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"""
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process ($clock, $reset) begin
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if (reset = '0') then
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if ($reset = '0') then
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$count <= (others => '0');
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elsif rising_edge($clock) then
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if (enable = '1') then
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if ($enable = '1') then
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$count <= $nextCount;
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end if;
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end if;
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