FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

.out

Browse Source
This commit is contained in:
jand 2004-01-03 12:26:17 +00:00
parent ebcd7c993d
commit fb9329436c
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
myhdl/test/toVerilog/Makefile
View File

@ -2,4 +2,4 @@ all:
python test_all.py
clean:
- rm *.o *.v *.pyc *~
- rm *.o *.out *.v *.pyc *~