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toVerilog is now a callable instance

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This commit is contained in:
jand 2005-09-09 09:15:07 +00:00
parent 60d6cc0142
commit fba110a473
2 changed files with 65 additions and 49 deletions
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2
myhdl/_toVerilog/_analyze.py
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@ -138,7 +138,9 @@ def _analyzeGens(top, genNames):
else: else:
f = g.gi_frame f = g.gi_frame
s = inspect.getsource(f) s = inspect.getsource(f)
#print s
s = s.lstrip() s = s.lstrip()
#print s
ast = compiler.parse(s) ast = compiler.parse(s)
#print ast #print ast
ast.sourcefile = inspect.getsourcefile(f) ast.sourcefile = inspect.getsourcefile(f)

24
myhdl/_toVerilog/_convert.py
View File

@ -38,7 +38,7 @@ import warnings
import myhdl import myhdl
from myhdl import * from myhdl import *
from myhdl import ToVerilogError, ToVerilogWarning from myhdl import ToVerilogError, ToVerilogWarning
from myhdl._extractHierarchy import _HierExtr, _findInstanceName, _isMem, _getMemInfo from myhdl._extractHierarchy import _HierExtr, _isMem, _getMemInfo
from myhdl._util import _flatten from myhdl._util import _flatten
from myhdl._always_comb import _AlwaysComb from myhdl._always_comb import _AlwaysComb
from myhdl._toVerilog import _error, _access, _kind,_context, \ from myhdl._toVerilog import _error, _access, _kind,_context, \
@ -54,7 +54,15 @@ def _checkArgs(arglist):
if not type(arg) in (GeneratorType, _AlwaysComb): if not type(arg) in (GeneratorType, _AlwaysComb):
raise ToVerilogError(_error.ArgType, arg) raise ToVerilogError(_error.ArgType, arg)
def toVerilog(func, *args, **kwargs):
class _ToVerilogConvertor(object):
__slots__ = ("name")
def __init__(self):
self.name = None
def __call__(self, func, *args, **kwargs):
global _converting global _converting
if _converting: if _converting:
return func(*args, **kwargs) # skip return func(*args, **kwargs) # skip
@ -68,12 +76,15 @@ def toVerilog(func, *args, **kwargs):
raise ToVerilogError(_error.FirstArgType, "got %s" % type(func)) raise ToVerilogError(_error.FirstArgType, "got %s" % type(func))
_converting = 1 _converting = 1
if self.name is None:
name = func.func_name
else:
name = str(self.name)
try: try:
# outer = inspect.getouterframes(inspect.currentframe())[1] # outer = inspect.getouterframes(inspect.currentframe())[1]
# name = _findInstanceName(outer) # name = _findInstanceName(outer)
name = func.func_name ## if name is None:
if name is None: ## raise ToVerilogError(_error.TopLevelName)
raise ToVerilogError(_error.TopLevelName)
h = _HierExtr(name, func, *args, **kwargs) h = _HierExtr(name, func, *args, **kwargs)
finally: finally:
_converting = 0 _converting = 0
@ -106,6 +117,9 @@ def toVerilog(func, *args, **kwargs):
return h.top return h.top
toVerilog = _ToVerilogConvertor()
def _writeModuleHeader(f, intf): def _writeModuleHeader(f, intf):
print >> f, "module %s (" % intf.name print >> f, "module %s (" % intf.name
b = StringIO() b = StringIO()