toVerilog is now a callable instance

myhdl/_toVerilog/_analyze.py

@@ -138,7 +138,9 @@ def _analyzeGens(top, genNames):
         else:
             f = g.gi_frame
             s = inspect.getsource(f)
+            #print s
             s = s.lstrip()
+            #print s
             ast = compiler.parse(s)
             #print ast
             ast.sourcefile = inspect.getsourcefile(f)

myhdl/_toVerilog/_convert.py

@@ -38,7 +38,7 @@ import warnings
 import myhdl
 from myhdl import *
 from myhdl import ToVerilogError, ToVerilogWarning
-from myhdl._extractHierarchy import _HierExtr, _findInstanceName, _isMem, _getMemInfo
+from myhdl._extractHierarchy import _HierExtr, _isMem, _getMemInfo
 from myhdl._util import _flatten
 from myhdl._always_comb import _AlwaysComb
 from myhdl._toVerilog import _error, _access, _kind,_context, \
@@ -54,7 +54,15 @@ def _checkArgs(arglist):
         if not type(arg) in (GeneratorType, _AlwaysComb):
             raise ToVerilogError(_error.ArgType, arg)
         
-def toVerilog(func, *args, **kwargs):
+
+class _ToVerilogConvertor(object):
+
+    __slots__ = ("name")
+
+    def __init__(self):
+        self.name = None
+
+    def __call__(self, func, *args, **kwargs):
         global _converting
         if _converting:
             return func(*args, **kwargs) # skip
@@ -68,12 +76,15 @@ def toVerilog(func, *args, **kwargs):
             raise ToVerilogError(_error.FirstArgType, "got %s" % type(func))
 
         _converting = 1
+        if self.name is None:
+            name = func.func_name
+        else:
+            name = str(self.name)
         try:
             # outer = inspect.getouterframes(inspect.currentframe())[1]
             # name = _findInstanceName(outer)
-        name = func.func_name
-        if name is None:
-            raise ToVerilogError(_error.TopLevelName)
+##             if name is None:
+##                 raise ToVerilogError(_error.TopLevelName)
             h = _HierExtr(name, func, *args, **kwargs)
         finally:
             _converting = 0
@@ -106,6 +117,9 @@ def toVerilog(func, *args, **kwargs):
         return h.top
     
 
+toVerilog = _ToVerilogConvertor()
+
+
 def _writeModuleHeader(f, intf):
     print >> f, "module %s (" % intf.name
     b = StringIO()