FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity

commented out print statements in _verify

Browse Source 
--HG--
branch : mep107
This commit is contained in:
Christopher Felton 2013-07-13 21:01:47 -05:00
parent 8c56ec9dc9
commit fc36a503fb
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
myhdl/conversion/_verify.py
View File

@ -140,7 +140,7 @@ class _VerificationClass(object):
except:
pass
print(analyze)
#print(analyze)
ret = subprocess.call(analyze, shell=True)
if ret != 0:
print >> sys.stderr, "Analysis failed"
@ -166,14 +166,14 @@ class _VerificationClass(object):
if elaborate is not None:
print(elaborate)
#print(elaborate)
ret = subprocess.call(elaborate, shell=True)
if ret != 0:
print >> sys.stderr, "Elaboration failed"
return ret
g = tempfile.TemporaryFile()
print(simulate)
#print(simulate)
ret = subprocess.call(simulate, stdout=g, shell=True)
# if ret != 0:
# print "Simulation run failed"