The future is now

cosimulation/icarus/test/test.py

@@ -1,6 +1,3 @@
-from __future__ import generators
-from __future__ import print_function
-
 from myhdl import Signal, Simulation, Cosimulation
 from myhdl import delay, intbv, now
 

cosimulation/test/test_bin2gray.py

@@ -1,5 +1,3 @@
-from __future__ import generators
-
 import unittest
 from unittest import TestCase
 

cosimulation/test/test_dff.py

@@ -1,5 +1,3 @@
-from __future__ import generators
-
 import unittest
 from unittest import TestCase
 import random

cosimulation/test/test_inc.py

@@ -1,5 +1,3 @@
-from __future__ import generators
-
 import unittest
 from unittest import TestCase
 import random

example/manual/queue.py

@@ -1,5 +1,3 @@
-from __future__ import generators
-
 import myhdl
 from myhdl import *
 

example/manual/rs232.py

@@ -1,5 +1,3 @@
-from __future__ import generators
-
 import sys
 from random import randrange
 

myhdl/_Cosimulation.py

@@ -18,8 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the Cosimulation class """
-from __future__ import absolute_import
-
 import sys
 import os
 #import shlex

myhdl/_ShadowSignal.py

@@ -21,8 +21,6 @@
 
 
 """
-from __future__ import absolute_import
-
 import warnings
 from copy import deepcopy
 

myhdl/_Signal.py

@@ -26,9 +26,6 @@ posedge -- callable to model a rising edge on a signal in a yield statement
 negedge -- callable to model a falling edge on a signal in a yield statement
 
 """
-from __future__ import absolute_import
-from __future__ import print_function
-
 from copy import copy, deepcopy
 
 from myhdl import _simulator as sim

myhdl/_Simulation.py

@@ -18,9 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the Simulation class """
-from __future__ import absolute_import
-from __future__ import print_function
-
 import os
 from operator import itemgetter
 from types import GeneratorType

myhdl/_Waiter.py

@@ -18,9 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the _Waiter class """
-from __future__ import absolute_import
-
-
 from types import GeneratorType
 
 import ast

myhdl/__init__.py

@@ -49,9 +49,6 @@ traceSignals -- function that enables signal tracing in a VCD file
 toVerilog -- function that converts a design to Verilog
 
 """
-from __future__ import absolute_import
-from __future__ import print_function
-
 __version__ = "0.10"
 
 

myhdl/_always.py

@@ -18,9 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always function. """
-from __future__ import absolute_import
-
-
 from types import FunctionType
 
 from myhdl import AlwaysError

myhdl/_always_comb.py

@@ -18,8 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always_comb function. """
-from __future__ import absolute_import
-
 from types import FunctionType
 
 from myhdl import AlwaysCombError

myhdl/_always_seq.py

@@ -18,9 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always_seq decorator. """
-from __future__ import absolute_import
-
-
 from types import FunctionType
 
 from myhdl import AlwaysError, intbv

myhdl/_block.py

@@ -18,8 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Block with the @block decorator function. """
-from __future__ import absolute_import, print_function
-
 import inspect
 
 #from functools import wraps

myhdl/_concat.py

@@ -22,8 +22,6 @@
 """ module with the concat function.
 
 """
-from __future__ import absolute_import
-
 from myhdl._intbv import intbv
 from myhdl._Signal import _Signal
 

myhdl/_delay.py

@@ -18,8 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module that provides the delay class."""
-from __future__ import absolute_import
-
 _errmsg = "arg of delay constructor should be a natural integeer"
 
 

myhdl/_enum.py

@@ -20,8 +20,6 @@
 """ Module that implements enum.
 
 """
-from __future__ import absolute_import
-
 from myhdl._bin import bin
 from myhdl._Signal import _Signal
 # from myhdl.conversion._VHDLNameValidation import _nameValid

myhdl/_extractHierarchy.py

@@ -20,9 +20,6 @@
 """ myhdl _extractHierarchy module.
 
 """
-from __future__ import absolute_import
-
-
 import sys
 import inspect
 import string

myhdl/_getHierarchy.py

@@ -21,8 +21,6 @@
 
 """
 
-from __future__ import absolute_import
-
 from myhdl._extractHierarchy import _Instance
 from myhdl._block import _Block
 

myhdl/_getcellvars.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import ast
 
 from myhdl._util import _flatten

myhdl/_instance.py

@@ -18,9 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the always function. """
-from __future__ import absolute_import
-
-
 import inspect
 from types import FunctionType
 

myhdl/_intbv.py

@@ -18,8 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the intbv class """
-from __future__ import absolute_import, division
-
 import builtins
 
 from myhdl._bin import bin

myhdl/_misc.py

@@ -24,9 +24,6 @@ instances -- function that returns instances in a generator function
 downrange -- function that returns a downward range
 
 """
-from __future__ import absolute_import
-
-
 import inspect
 
 from myhdl._Cosimulation import Cosimulation

myhdl/_modbv.py

@@ -18,8 +18,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Module with the modbv class """
-from __future__ import absolute_import
-
 from ._intbv import intbv
 
 

myhdl/_resolverefs.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import ast
 import itertools
 from types import FunctionType

myhdl/_traceSignals.py

@@ -20,10 +20,6 @@
 """ myhdl traceSignals block.
 
 """
-from __future__ import absolute_import
-from __future__ import print_function
-
-
 import sys
 import time
 import os

myhdl/_tristate.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import warnings
 
 from myhdl._Signal import _Signal, _DelayedSignal

myhdl/_util.py

@@ -20,9 +20,6 @@
 """ Module with utilility objects for MyHDL.
 
 """
-from __future__ import absolute_import
-from __future__ import print_function
-
 import __future__
 import ast
 import sys

myhdl/conversion/__init__.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 from ._verify import verify, analyze, registerSimulator
 from ._toVerilog import toVerilog
 from ._toVHDL import toVHDL

myhdl/conversion/_analyze.py

@@ -20,8 +20,6 @@
 """ MyHDL conversion analysis module.
 
 """
-from __future__ import absolute_import, print_function
-
 import inspect
 # import compiler
 # from compiler import ast as astNode

myhdl/conversion/_misc.py

@@ -20,9 +20,6 @@
 """ myhdl toVerilog package.
 
 """
-from __future__ import absolute_import
-
-
 import ast
 
 from myhdl import ConversionError

myhdl/conversion/_toVHDL.py

@@ -20,9 +20,6 @@
 """ myhdl toVHDL conversion module.
 
 """
-from __future__ import absolute_import
-from __future__ import print_function
-
 import sys
 import math
 import os

myhdl/conversion/_toVHDLPackage.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 #  This file is part of the myhdl library, a Python package for using
 #  Python as a Hardware Description Language.
 #

myhdl/conversion/_toVerilog.py

@@ -20,10 +20,6 @@
 """ myhdl toVerilog conversion module.
 
 """
-from __future__ import absolute_import
-from __future__ import print_function
-
-
 import sys
 import math
 import os

myhdl/conversion/_verify.py

@@ -1,5 +1,3 @@
-from __future__ import absolute_import
-from __future__ import print_function
 import sys
 import os
 import tempfile

myhdl/debug.py

@@ -1,6 +1,3 @@
-from __future__ import absolute_import
-from __future__ import print_function
-
 import platform
 
 from . import __version__

myhdl/test/bugs/test_bug_1740778.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/bugs/test_bug_1835792.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/bugs/test_bug_1835797.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/bugs/test_bug_1837003.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl import ConversionError

myhdl/test/bugs/test_bug_28.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/bugs/test_bug_3529686.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/bugs/test_bug_3577799.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl.conversion import analyze

myhdl/test/bugs/test_bug_39.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl.conversion import verify

myhdl/test/bugs/test_bug_42.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 #! /usr/bin/env python
 
 import myhdl

myhdl/test/bugs/test_bug_42_2.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 #! /usr/bin/env python
 
 import myhdl

myhdl/test/bugs/test_bug_43.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 #! /usr/bin/env python
 
 import myhdl

myhdl/test/bugs/test_bug_44.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/bugs/test_bug_aj1s.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl.conversion import verify

myhdl/test/bugs/test_bug_boolconst.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/bugs/test_bug_boolop.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/bugs/test_bug_enum_toVHDL.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/bugs/test_bug_enum_toVHDL_2.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/bugs/test_issue_10.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 #!/usr/bin/python2.7-32
 # -*- coding: utf-8 -*-
 

myhdl/test/bugs/test_issue_104.py

@@ -1,4 +1,3 @@
-from __future__ import print_function
 import pytest
 from myhdl import Simulation, delay, SimulationError, instance, now
 from myhdl._Simulation import _error

myhdl/test/bugs/test_issue_10_2.py

@@ -2,8 +2,6 @@
 # -*- coding: utf-8 -*-
 """Failed VHDL code example
 """
-from __future__ import absolute_import
-
 import myhdl
 from myhdl import *
 from myhdl.conversion import verify

myhdl/test/bugs/test_issue_117.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl.conversion import analyze

myhdl/test/bugs/test_issue_122.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl.conversion import verify 

myhdl/test/bugs/test_issue_127.py

@@ -2,8 +2,6 @@
 
 # http://www.myhdl.org/examples/bitonic/
 
-from __future__ import absolute_import
-
 import unittest
 from random import randrange
 

myhdl/test/bugs/test_issue_13.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl.conversion import analyze

myhdl/test/bugs/test_issue_133.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl.conversion import verify 

myhdl/test/bugs/test_issue_134.py

@@ -3,7 +3,6 @@ When an interface signal gets passed into a function, it
 can get renamed to the name of the argument. When the
 function is called multiple times, this causes name collisions """
 
-from __future__ import absolute_import
 import pytest
 import myhdl
 from myhdl import *

myhdl/test/bugs/test_issue_167.py

@@ -2,8 +2,6 @@
 
 # http://www.myhdl.org/examples/bitonic/
 
-from __future__ import absolute_import
-
 import unittest
 from random import randrange
 

myhdl/test/bugs/test_issue_18.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl.conversion import analyze

myhdl/test/bugs/test_issue_40.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 #! /usr/bin/env python
 
 import myhdl

myhdl/test/bugs/test_issue_9.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/bugs/test_issue_98.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl.conversion import analyze

myhdl/test/conversion/general/test_ShadowSignal.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/conversion/general/test_adapter.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/conversion/general/test_bin2gray.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 

myhdl/test/conversion/general/test_case.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/conversion/general/test_constants.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 

myhdl/test/conversion/general/test_dec.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 import random

myhdl/test/conversion/general/test_errors.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl import ConversionError

myhdl/test/conversion/general/test_fsm.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 

myhdl/test/conversion/general/test_hec.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 from random import randrange

myhdl/test/conversion/general/test_inc.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import sys
 import os
 path = os.path

myhdl/test/conversion/general/test_initial_values.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 from random import randrange
 
 from myhdl import *

myhdl/test/conversion/general/test_intbv_signed.py

@@ -19,8 +19,6 @@
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 """ Run the intbv.signed() unit tests. """
-from __future__ import absolute_import
-
 import myhdl
 from myhdl import *
 

myhdl/test/conversion/general/test_interfaces1.py

@@ -1,5 +1,3 @@
-from __future__ import absolute_import
-
 from myhdl import (block, Signal, ResetSignal, intbv, always_seq,
                    instance, delay, StopSimulation, )
 

myhdl/test/conversion/general/test_interfaces3.py

@@ -1,5 +1,3 @@
-from __future__ import absolute_import
-
 import sys
 
 import myhdl

myhdl/test/conversion/general/test_listofsigs.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl import ConversionError

myhdl/test/conversion/general/test_loops.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 from random import randrange

myhdl/test/conversion/general/test_method.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import sys
 import myhdl
 from myhdl import *

myhdl/test/conversion/general/test_nonlocal.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 

myhdl/test/conversion/general/test_numass.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 from random import randrange
 
 import myhdl

myhdl/test/conversion/general/test_print.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl import ConversionError

myhdl/test/conversion/general/test_ram.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 import unittest

myhdl/test/conversion/general/test_randscrambler.py

@@ -1,5 +1,3 @@
-from __future__ import absolute_import
-
 import os
 path = os.path
 import unittest

myhdl/test/conversion/general/test_rom.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 from random import randrange

myhdl/test/conversion/general/test_ternary.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 import unittest

myhdl/test/conversion/general/test_toplevel_interfaces.py

@@ -4,8 +4,6 @@ Created on 23 aug. 2018
 @author: josy
 '''
 
-from __future__ import print_function
-
 from myhdl import Signal, intbv, block, always_comb, always_seq, ResetSignal, instance, \
                     delay, StopSimulation
 

myhdl/test/conversion/general/test_toplevel_method.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import sys
 import myhdl
 from myhdl import *

myhdl/test/conversion/toVHDL/test_custom.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 

myhdl/test/conversion/toVHDL/test_enum.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from random import randrange

myhdl/test/conversion/toVHDL/test_keywords.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import myhdl
 from myhdl import *
 from myhdl import ToVHDLWarning

myhdl/test/conversion/toVHDL/test_loops.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path
 from random import randrange

myhdl/test/conversion/toVHDL/test_newcustom.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import os
 path = os.path