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ops
This commit is contained in:
jand
parent
045e66ebb8
commit
fce4c7e7e5
@ -767,6 +767,8 @@ class _AnalyzeVisitor(_ConversionMixin):
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self.visit(node.body, *args)
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self.refStack.pop()
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y = node.body.nodes[0]
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if isinstance(y, astNode.Discard):
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y = y.expr
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if node.test.obj == True and \
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isinstance(y, astNode.Yield) and \
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not self.ast.hasYield > 1 and \
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@ -382,44 +382,28 @@ class _ConvertVisitor(_ConversionMixin):
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pre, suf = "", ""
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prel, sufl = "", ""
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prer, sufr = "", ""
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if isinstance(node.vhd, vhd_type):
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ts = node.vhd.size
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if isinstance(node.left.vhd, vhd_int) and isinstance(node.right.vhd, vhd_int):
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if isinstance(node.vhd, vhd_unsigned):
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n, o, l, r = node.vhd, node.vhdOri, node.left.vhd, node.right.vhd
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ns, os, ls, rs = n.size, o.size, l.size, r.size
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ds = ns - os
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if isinstance(o, vhd_int):
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if isinstance(n, vhd_unsigned):
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pre, suf = "to_unsigned(", ", %s)" % node.vhd.size
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elif isinstance(node.vhd, vhd_signed):
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elif isinstance(n, vhd_signed):
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pre, suf = "to_signed(", ", %s)" % node.vhd.size
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elif isinstance(node.vhd, vhd_int):
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elif isinstance(n, vhd_int):
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pass
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else:
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raise NotImplementedError
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elif isinstance(node.left.vhd, vhd_unsigned) and isinstance(node.right.vhd, vhd_int):
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if op == '*':
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ns = 2 * node.left.vhd.size
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else:
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ns = node.left.vhd.size
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ds = ts - ns
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if isinstance(node.vhd, vhd_unsigned):
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if ds > 0:
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prel, sufl = "resize(", ", %s)" % node.vhd.size
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elif ds < 0:
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pre, suf = "resize(", ", %s)" % node.vhd.size
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else:
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assert NotImplementedError
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elif isinstance(node.left.vhd, vhd_unsigned) and isinstance(node.right.vhd, vhd_unsigned):
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if op == '*':
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ns = node.left.vhd.size + node.right.vhd.size
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else:
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ns = max(node.left.vhd.size, node.right.vhd.size)
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ds = ts - ns
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if isinstance(node.vhd, vhd_unsigned):
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if ds > 0:
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prel, sufl = "resize(", ", %s)" % ts
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elif ds < 0:
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pre, suf = "resize(", ", %s)" % ts
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else:
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assertNotImplementedError
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self.raiseError(node, "Not implemented")
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elif isinstance(l, vhd_unsigned) and isinstance(r, (vhd_int, vhd_unsigned)):
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## if op == '+':
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## print ns
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## print os
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## print ds
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if ds > 0:
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prel, sufl = "resize(", ", %s)" % ns
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elif ds < 0:
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pre, suf = "resize(", ", %s)" % ns
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context = None
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self.write(pre)
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self.write("(")
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@ -642,13 +626,13 @@ class _ConvertVisitor(_ConversionMixin):
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"-=" : "-",
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"*=" : "*",
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"//=" : "/",
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"%=" : "%",
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"%=" : "mod",
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"**=" : "**",
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"|=" : "|",
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"|=" : "or",
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">>=" : ">>>",
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"<<=" : "<<",
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"&=" : "&",
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"^=" : "^"
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"&=" : "and",
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"^=" : "xor"
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}
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if node.op not in opmap:
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self.raiseError(node, _error.NotSupported,
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@ -1006,7 +990,10 @@ class _ConvertVisitor(_ConversionMixin):
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elif isinstance(node.vhd, vhd_unsigned):
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if vhd.size != node.vhd.size:
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s = "resize(%s, %s)" % (n, node.vhd.size)
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elif isinstance(node.vhd, vhd_boolean):
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s = "(%s /= 0)" % n
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else:
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print node.vhd
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raise NotImplementedError
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@ -1197,9 +1184,11 @@ class _ConvertAlwaysVisitor(_ConvertVisitor):
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def visitFunction(self, node, *args):
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w = node.code.nodes[-1]
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assert isinstance(w.body.nodes[0], astNode.Yield)
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sl = w.body.nodes[0].value
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senslist = w.body.nodes[0].senslist
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y = w.body.nodes[0]
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if isinstance(y, astNode.Discard):
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y = y.expr
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assert isinstance(y, astNode.Yield)
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senslist = y.senslist
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senslist = self.manageEdges(w.body.nodes[1], senslist)
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singleEdge = (len(senslist) == 1) and isinstance(senslist[0], _WaiterList)
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self.write("%s: process (" % self.ast.name)
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@ -1472,15 +1461,18 @@ class vhd_boolean(vhd_type):
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self.size = 1
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def toStr(self, constr=True):
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return 'boolean'
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class vhd_vector(vhd_type):
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pass
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class vhd_unsigned(vhd_type):
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class vhd_unsigned(vhd_vector):
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def toStr(self, constr=True):
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if constr:
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return "unsigned(%s downto 0)" % (self.size-1)
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else:
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return "unsigned"
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class vhd_signed(vhd_type):
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class vhd_signed(vhd_vector):
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def toStr(self, constr=True):
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if constr:
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return "signed(%s downto 0)" % (self.size-1)
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@ -1594,20 +1586,46 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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def binaryOp(self, node, op=None):
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self.visit(node.left)
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self.visit(node.right)
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r = node.right.vhd
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l = node.left.vhd
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if op in ('+', '-', '%'):
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s = max(l.size, r.size)
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elif op in ('*',):
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s = l.size + r.size
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r, l = node.right.vhd, node.left.vhd
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rs, ls = r.size, l.size
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if isinstance(r, vhd_signed) and isinstance(r, vhd_unsigned):
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rs += 1
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if isinstance(r, vhd_unsigned) and isinstance(r, vhd_signed):
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ls += 1
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if isinstance(r, vhd_vector) and isinstance(l, vhd_vector):
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if op in ('+', '-'):
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s = max(ls, rs)
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elif op == '%':
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s = rs
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elif op == '/':
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s = ls
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elif op == '*':
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s = ls + rs
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else:
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self.raiseError(node, "Not implemented: %s" % op)
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elif isinstance(l, vhd_vector) and isinstance(r, vhd_int):
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if op in ('+', '-', '%', '/'):
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s = ls
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elif op == '*':
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s = 2 * ls
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else:
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self.raiseError(node, "Not implemented")
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elif isinstance(l, vhd_int) and isinstance(r, vhd_vector):
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if op in ('+', '-', '%', '/'):
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s = rs
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elif op == '*':
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s = 2 * rs
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else:
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self.raiseError(node, "Not implemented: %s" % op)
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if isinstance(r, vhd_int) and isinstance(l, vhd_int):
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node.vhd = vhd_int()
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elif isinstance(r, (vhd_signed, vhd_int)) and isinstance(l, (vhd_signed, vhd_int)):
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node.vhd = vhd_signed(max(l.size, r.size))
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node.vhd = vhd_signed(s)
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elif isinstance(r, (vhd_unsigned, vhd_int)) and isinstance(l, (vhd_unsigned, vhd_int)):
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node.vhd = vhd_unsigned(max(l.size, r.size))
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node.vhd = vhd_unsigned(s)
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else:
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node.vhd = vhd_int()
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node.vhdOri = node.vhd
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def visitAdd(self, node):
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self.binaryOp(node, op='+')
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@ -1616,7 +1634,9 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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def visitMod(self, node):
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self.binaryOp(node, op='%')
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def visitMul(self, node):
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self.binaryOp(node, op='+')
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self.binaryOp(node, op='*')
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def visitFloorDiv(self, node):
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self.binaryOp(node, op='/')
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def multiBitOp(self, node):
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@ -1687,5 +1707,9 @@ def _annotateTypes(genlist):
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v = _AnnotateTypesVisitor(ast)
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compiler.walk(ast, v)
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@ -32,7 +32,7 @@ import inspect
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import compiler
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from compiler import ast as astNode
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from sets import Set
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from types import GeneratorType, FunctionType, ClassType
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from types import GeneratorType, FunctionType, ClassType, TypeType
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from cStringIO import StringIO
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import __builtin__
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import warnings
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@ -529,7 +529,7 @@ class _ConvertVisitor(_ConversionMixin):
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elif f is intbv:
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self.visit(node.args[0])
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return
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elif type(f) is ClassType and issubclass(f, Exception):
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elif type(f) in (ClassType, TypeType) and issubclass(f, Exception):
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self.write(f.__name__)
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elif f in (posedge, negedge):
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opening, closing = ' ', ''
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@ -769,7 +769,7 @@ class _ConvertVisitor(_ConversionMixin):
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s = m.name
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elif isinstance(obj, EnumItemType):
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s = obj._toVerilog()
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elif type(obj) is ClassType and issubclass(obj, Exception):
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elif type(obj) in (ClassType, TypeType) and issubclass(obj, Exception):
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s = n
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else:
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self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj)))
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@ -905,8 +905,11 @@ class _ConvertAlwaysVisitor(_ConvertVisitor):
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def visitFunction(self, node, *args):
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w = node.code.nodes[-1]
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assert isinstance(w.body.nodes[0], astNode.Yield)
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sl = w.body.nodes[0].value
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y = w.body.nodes[0]
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if isinstance(y, astNode.Discard):
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y = y.expr
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assert isinstance(y, astNode.Yield)
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sl = y.value
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self.write("always @(")
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self.visit(sl, _context.YIELD)
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self.write(") begin: %s" % self.ast.name)
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@ -127,7 +127,7 @@ class _VerificationClass(object):
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print >> sys.stderr, "Conversion verification succeeded"
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else:
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print >> sys.stderr, "Conversion verification failed"
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print >> sys.stderr, s ,
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# print >> sys.stderr, s ,
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return 1
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return 0
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@ -32,12 +32,13 @@ def binaryOps(
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left, right):
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while 1:
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yield left, right
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## Bitand.next = left & right
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## Bitor.next = left | right
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## Bitxor.next = left ^ right
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## if right != 0:
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## FloorDiv.next = left // right
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if left < 256 and right < 40:
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Bitand.next = left & right
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Bitor.next = left | right
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Bitxor.next = left ^ right
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if right != 0:
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FloorDiv.next = left // right
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## if left < 256 and right < 40:
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if left < 256 and right < 26: # fails in ghdl for > 26
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LeftShift.next = left << right
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## if right != 0:
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## Modulo.next = left % right
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@ -136,19 +137,16 @@ def binaryBench(m, n):
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while True:
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yield left, right
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yield delay(1)
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# print "%s %s %s %s" % (left, right, Boolor, Boolor_v)
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## self.assertEqual(Bitand, Bitand_v)
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## self.assertEqual(Bitor, Bitor_v)
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## self.assertEqual(Bitxor, Bitxor_v)
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## self.assertEqual(FloorDiv, FloorDiv_v)
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print Bitand
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print Bitor
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print Bitxor
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print FloorDiv
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print LeftShift
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## print Modulo, Modulo_v)
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## # print Pow, Pow_v)
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## self.assertEqual(Modulo, Modulo_v)
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## # self.assertEqual(Pow, Pow_v)
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print RightShift
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print Mul
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print Sub
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@ -164,225 +162,185 @@ def binaryBench(m, n):
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return binops, stimulus(), check()
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def testBinary():
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# for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
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for m, n in ((4, 4,),):
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yield checkBinary, m, n
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def checkBinary(m, n):
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assert verify(binaryBench, m, n) == 0
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def testBinary():
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for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
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# for m, n in ((2, 6),):
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yield checkBinary, m, n
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## def multiOps(
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## Bitand,
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## Bitor,
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## Bitxor,
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## Booland,
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## Boolor,
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## argm, argn, argp):
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## while 1:
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## yield argm, argn, argp
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## Bitand.next = argm & argn & argp
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## Bitor.next = argm | argn | argp
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## Bitxor.next = argm ^ argn ^ argp
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## Booland.next = bool(argm) and bool(argn) and bool(argp)
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## Boolor.next = bool(argm) and bool(argn) and bool(argp)
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## def multiOps_v( name,
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## Bitand,
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## Bitor,
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## Bitxor,
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## Booland,
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## Boolor,
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## argm, argn, argp):
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def multiOps(
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Bitand,
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Bitor,
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Bitxor,
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Booland,
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Boolor,
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argm, argn, argp):
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while 1:
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yield argm, argn, argp
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Bitand.next = argm & argn & argp
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Bitor.next = argm | argn | argp
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Bitxor.next = argm ^ argn ^ argp
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Booland.next = bool(argm) and bool(argn) and bool(argp)
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Boolor.next = bool(argm) and bool(argn) and bool(argp)
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## return setupCosimulation(**locals())
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## class TestMultiOps(TestCase):
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## def multiBench(self, m, n, p):
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def multiBench(m, n, p):
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## M = 2**m
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## N = 2**n
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## P = 2**p
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M = 2**m
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N = 2**n
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P = 2**p
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## argm = Signal(intbv(0)[m:])
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## argn = Signal(intbv(0)[n:])
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## argp = Signal(intbv(0)[p:])
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## Bitand = Signal(intbv(0)[max(m, n, p):])
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## Bitand_v = Signal(intbv(0)[max(m, n, p):])
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## Bitor = Signal(intbv(0)[max(m, n, p):])
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## Bitor_v = Signal(intbv(0)[max(m, n, p):])
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## Bitxor = Signal(intbv(0)[max(m, n, p):])
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## Bitxor_v = Signal(intbv(0)[max(m, n, p):])
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## Booland, Boolor = [Signal(bool()) for i in range(2)]
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## Booland_v, Boolor_v, = [Signal(bool()) for i in range(2)]
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Q = min(M, N, P)
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seqQ = tuple(range(1, Q))
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seqM = tuple([randrange(M) for i in range(NRTESTS)])
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seqN = tuple([randrange(N) for i in range(NRTESTS)])
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seqP = tuple([randrange(P) for i in range(NRTESTS)])
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## multiops = toVerilog(multiOps,
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## Bitand,
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## Bitor,
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## Bitxor,
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## Booland,
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## Boolor,
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## argm, argn, argp)
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## multiops_v = multiOps_v(multiOps.func_name,
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## Bitand_v,
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## Bitor_v,
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## Bitxor_v,
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## Booland_v,
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## Boolor_v,
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## argm, argn, argp)
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argm = Signal(intbv(0)[m:])
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argn = Signal(intbv(0)[n:])
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argp = Signal(intbv(0)[p:])
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Bitand = Signal(intbv(0)[max(m, n, p):])
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Bitor = Signal(intbv(0)[max(m, n, p):])
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Bitxor = Signal(intbv(0)[max(m, n, p):])
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Booland, Boolor = [Signal(bool()) for i in range(2)]
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## def stimulus():
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## for i in range(min(M, N, P)):
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## # print i
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## argm.next = intbv(i)
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## argn.next = intbv(i)
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## argp.next = intbv(i)
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## yield delay(10)
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## for i in range(100):
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## argm.next = randrange(M)
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## argn.next = randrange(N)
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## argp.next = randrange(P)
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## yield delay(10)
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## for j, k, l in ((0, 0, 0), (0, 0, P-1), (0, N-1, P-1),
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## (M-1, 0, 0), (M-1, 0, P-1), (M-1, N-1, 0),
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## (0, N-1, 0), (M-1, N-1, P-1)):
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## argm.next = j
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## argn.next = k
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## argp.next = l
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## yield delay(10)
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multiops = multiOps(Bitand,
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Bitor,
|
||||
Bitxor,
|
||||
Booland,
|
||||
Boolor,
|
||||
argm, argn, argp)
|
||||
|
||||
## def check():
|
||||
## while 1:
|
||||
## yield argm, argn, argp
|
||||
## yield delay(1)
|
||||
## # print "%s %s %s %s %s" % (argm, argn, argp, Bitxor, Bitxor_v)
|
||||
## self.assertEqual(Bitand, Bitand_v)
|
||||
## self.assertEqual(Bitor, Bitor_v)
|
||||
## self.assertEqual(Bitxor, Bitxor_v)
|
||||
## self.assertEqual(Booland, Booland_v)
|
||||
## self.assertEqual(Boolor, Boolor_v)
|
||||
def stimulus():
|
||||
for i in range(len(seqQ)):
|
||||
argm.next = seqQ[i]
|
||||
argn.next = seqQ[i]
|
||||
argp.next = seqQ[i]
|
||||
yield delay(10)
|
||||
for i in range(NRTESTS):
|
||||
argm.next = seqM[i]
|
||||
argn.next = seqN[i]
|
||||
argp.next = seqP[i]
|
||||
yield delay(10)
|
||||
## for j, k, l in ((0, 0, 0), (0, 0, P-1), (0, N-1, P-1),
|
||||
## (M-1, 0, 0), (M-1, 0, P-1), (M-1, N-1, 0),
|
||||
## (0, N-1, 0), (M-1, N-1, P-1)):
|
||||
## argm.next = j
|
||||
## argn.next = k
|
||||
## argp.next = l
|
||||
## yield delay(10)
|
||||
|
||||
## return multiops, multiops_v, stimulus(), check()
|
||||
def check():
|
||||
while 1:
|
||||
yield argm, argn, argp
|
||||
yield delay(1)
|
||||
|
||||
print Bitand
|
||||
print Bitor
|
||||
print Bitxor
|
||||
print int(Booland)
|
||||
print int(Boolor)
|
||||
|
||||
return multiops, stimulus(), check()
|
||||
|
||||
def checkMultiOps(m, n, p):
|
||||
assert verify(multiBench, m, n, p) == 0
|
||||
|
||||
def testMultiOps():
|
||||
for m, n, p in ((4, 4, 4,), (5, 3, 2), (3, 4, 6), (3, 7, 4)):
|
||||
yield checkMultiOps, m, n, p
|
||||
|
||||
|
||||
def unaryOps(
|
||||
Not_kw,
|
||||
Invert,
|
||||
UnaryAdd,
|
||||
UnarySub,
|
||||
arg):
|
||||
while 1:
|
||||
yield arg
|
||||
Not_kw.next = not arg
|
||||
Invert.next = ~arg
|
||||
# unary operators not supported ?
|
||||
#UnaryAdd.next = +arg
|
||||
# UnarySub.next = --arg
|
||||
|
||||
def unaryBench(m):
|
||||
|
||||
M = 2**m
|
||||
seqM = tuple([randrange(M) for i in range(NRTESTS)])
|
||||
|
||||
arg = Signal(intbv(0)[m:])
|
||||
Not_kw = Signal(bool(0))
|
||||
Invert = Signal(intbv(0)[m:])
|
||||
UnaryAdd = Signal(intbv(0)[m:])
|
||||
UnarySub = Signal(intbv(0)[m:])
|
||||
|
||||
unaryops = unaryOps(Not_kw,
|
||||
Invert,
|
||||
UnaryAdd,
|
||||
UnarySub,
|
||||
arg)
|
||||
|
||||
def stimulus():
|
||||
for i in range(NRTESTS):
|
||||
arg.next = seqM[i]
|
||||
yield delay(10)
|
||||
raise StopSimulation
|
||||
|
||||
def check():
|
||||
while 1:
|
||||
yield arg
|
||||
yield delay(1)
|
||||
print int(Not_kw)
|
||||
print Invert
|
||||
# check unary operator support in vhdl
|
||||
# print UnaryAdd
|
||||
# print UnarySub
|
||||
|
||||
return unaryops, stimulus(), check()
|
||||
|
||||
def checkUnaryOps(m):
|
||||
assert verify(unaryBench, m) == 0
|
||||
|
||||
|
||||
## def testMultiOps(self):
|
||||
## for m, n, p in ((4, 4, 4,), (5, 3, 2), (3, 4, 6), (3, 7, 4)):
|
||||
## sim = self.multiBench(m, n, p)
|
||||
## Simulation(sim).run()
|
||||
def testUnaryOps():
|
||||
for m in (4, 7):
|
||||
yield checkUnaryOps, m
|
||||
|
||||
|
||||
|
||||
## def unaryOps(
|
||||
## Not,
|
||||
## Invert,
|
||||
## UnaryAdd,
|
||||
## UnarySub,
|
||||
## arg):
|
||||
## while 1:
|
||||
## yield arg
|
||||
## Not.next = not arg
|
||||
## Invert.next = ~arg
|
||||
## UnaryAdd.next = +arg
|
||||
## UnarySub.next = --arg
|
||||
|
||||
## def unaryOps_v(name,
|
||||
## Not,
|
||||
## Invert,
|
||||
## UnaryAdd,
|
||||
## UnarySub,
|
||||
## arg):
|
||||
## return setupCosimulation(**locals())
|
||||
|
||||
|
||||
|
||||
## class TestUnaryOps(TestCase):
|
||||
|
||||
## def unaryBench(self, m):
|
||||
|
||||
## M = 2**m
|
||||
|
||||
## arg = Signal(intbv(0)[m:])
|
||||
## Not = Signal(bool(0))
|
||||
## Not_v = Signal(bool(0))
|
||||
## Invert = Signal(intbv(0)[m:])
|
||||
## Invert_v = Signal(intbv(0)[m:])
|
||||
## UnaryAdd = Signal(intbv(0)[m:])
|
||||
## UnaryAdd_v = Signal(intbv(0)[m:])
|
||||
## UnarySub = Signal(intbv(0)[m:])
|
||||
## UnarySub_v = Signal(intbv(0)[m:])
|
||||
|
||||
## unaryops = toVerilog(unaryOps,
|
||||
## Not,
|
||||
## Invert,
|
||||
## UnaryAdd,
|
||||
## UnarySub,
|
||||
## arg)
|
||||
## unaryops_v = unaryOps_v(unaryOps.func_name,
|
||||
## Not_v,
|
||||
## Invert_v,
|
||||
## UnaryAdd_v,
|
||||
## UnarySub_v,
|
||||
## arg)
|
||||
|
||||
## def stimulus():
|
||||
## for i in range(M):
|
||||
## arg.next = intbv(i)
|
||||
## yield delay(10)
|
||||
## for i in range(100):
|
||||
## arg.next = randrange(M)
|
||||
## yield delay(10)
|
||||
## raise StopSimulation
|
||||
|
||||
## def check():
|
||||
## while 1:
|
||||
## yield arg
|
||||
## yield delay(1)
|
||||
## self.assertEqual(Not, Not_v)
|
||||
## self.assertEqual(Invert, Invert_v)
|
||||
## self.assertEqual(UnaryAdd, UnaryAdd_v)
|
||||
## self.assertEqual(UnarySub, UnarySub_v)
|
||||
|
||||
## return unaryops, unaryops_v, stimulus(), check()
|
||||
|
||||
## def testUnaryOps(self):
|
||||
## for m in (4, 7):
|
||||
## sim = self.unaryBench(m)
|
||||
## Simulation(sim).run()
|
||||
|
||||
|
||||
## def augmOps(
|
||||
## Bitand,
|
||||
## Bitor,
|
||||
## Bitxor,
|
||||
## FloorDiv,
|
||||
## LeftShift,
|
||||
## Modulo,
|
||||
## Mul,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum,
|
||||
## left, right):
|
||||
## var = intbv(0)[max(64, len(left) + len(right)):]
|
||||
## while 1:
|
||||
## yield left, right
|
||||
## var[:] = left
|
||||
## var &= right
|
||||
## Bitand.next = var
|
||||
## var[:] = left
|
||||
## var |= right
|
||||
## Bitor.next = var
|
||||
## var[:] = left
|
||||
## var ^= left
|
||||
## Bitxor.next = var
|
||||
## if right != 0:
|
||||
## var[:] = left
|
||||
## var //= right
|
||||
## FloorDiv.next = var
|
||||
def augmOps( Bitand,
|
||||
Bitor,
|
||||
Bitxor,
|
||||
FloorDiv,
|
||||
LeftShift,
|
||||
Modulo,
|
||||
Mul,
|
||||
RightShift,
|
||||
Sub,
|
||||
Sum,
|
||||
left, right):
|
||||
var = intbv(0)[max(64, len(left) + len(right)):]
|
||||
while True:
|
||||
yield left, right
|
||||
var[:] = left
|
||||
var &= right
|
||||
Bitand.next = var
|
||||
var[:] = left
|
||||
var |= right
|
||||
Bitor.next = var
|
||||
var[:] = left
|
||||
var ^= left
|
||||
Bitxor.next = var
|
||||
if right != 0:
|
||||
var[:] = left
|
||||
var //= right
|
||||
# FloorDiv.next = var
|
||||
## if left < 256 and right < 40:
|
||||
## var[:] = left
|
||||
## var <<= right
|
||||
@ -391,126 +349,90 @@ def checkBinary(m, n):
|
||||
## var[:] = left
|
||||
## var %= right
|
||||
## Modulo.next = var
|
||||
## var[:] = left
|
||||
## var *= right
|
||||
## Mul.next = var
|
||||
## var[:] = left
|
||||
var[:] = left
|
||||
var *= right
|
||||
Mul.next = var
|
||||
var[:] = left
|
||||
## var >>= right
|
||||
## RightShift.next = var
|
||||
## if left >= right:
|
||||
## var[:] = left
|
||||
## var -= right
|
||||
## Sub.next = var
|
||||
## var[:] = left
|
||||
## var += right
|
||||
## Sum.next = var
|
||||
if left >= right:
|
||||
var[:] = left
|
||||
var -= right
|
||||
Sub.next = var
|
||||
var[:] = left
|
||||
var += right
|
||||
Sum.next = var
|
||||
|
||||
|
||||
|
||||
|
||||
## def augmOps_v( name,
|
||||
## Bitand,
|
||||
## Bitor,
|
||||
## Bitxor,
|
||||
## FloorDiv,
|
||||
## LeftShift,
|
||||
## Modulo,
|
||||
## Mul,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum,
|
||||
## left, right):
|
||||
## return setupCosimulation(**locals())
|
||||
def augmBench(m, n):
|
||||
|
||||
## class TestAugmOps(TestCase):
|
||||
|
||||
## def augmBench(self, m, n):
|
||||
|
||||
## M = 2**m
|
||||
## N = 2**n
|
||||
|
||||
## left = Signal(intbv(0)[m:])
|
||||
## right = Signal(intbv(0)[n:])
|
||||
## Bitand = Signal(intbv(0)[max(m, n):])
|
||||
## Bitand_v = Signal(intbv(0)[max(m, n):])
|
||||
## Bitor = Signal(intbv(0)[max(m, n):])
|
||||
## Bitor_v = Signal(intbv(0)[max(m, n):])
|
||||
## Bitxor = Signal(intbv(0)[max(m, n):])
|
||||
## Bitxor_v = Signal(intbv(0)[max(m, n):])
|
||||
## FloorDiv = Signal(intbv(0)[m:])
|
||||
## FloorDiv_v = Signal(intbv(0)[m:])
|
||||
## LeftShift = Signal(intbv(0)[64:])
|
||||
## LeftShift_v = Signal(intbv(0)[64:])
|
||||
## Modulo = Signal(intbv(0)[m:])
|
||||
## Modulo_v = Signal(intbv(0)[m:])
|
||||
## Mul = Signal(intbv(0)[m+n:])
|
||||
## Mul_v = Signal(intbv(0)[m+n:])
|
||||
## RightShift = Signal(intbv(0)[m:])
|
||||
## RightShift_v = Signal(intbv(0)[m:])
|
||||
## Sub = Signal(intbv(0)[max(m, n):])
|
||||
## Sub_v = Signal(intbv(0)[max(m, n):])
|
||||
## Sum = Signal(intbv(0)[max(m, n)+1:])
|
||||
## Sum_v = Signal(intbv(0)[max(m, n)+1:])
|
||||
|
||||
## augmops = toVerilog(augmOps,
|
||||
## Bitand,
|
||||
## Bitor,
|
||||
## Bitxor,
|
||||
## FloorDiv,
|
||||
## LeftShift,
|
||||
## Modulo,
|
||||
## Mul,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum,
|
||||
## left, right)
|
||||
## augmops_v = augmOps_v( augmOps.func_name,
|
||||
## Bitand_v,
|
||||
## Bitor_v,
|
||||
## Bitxor_v,
|
||||
## FloorDiv_v,
|
||||
## LeftShift_v,
|
||||
## Modulo_v,
|
||||
## Mul_v,
|
||||
## RightShift_v,
|
||||
## Sub_v,
|
||||
## Sum_v,
|
||||
## left, right)
|
||||
|
||||
## def stimulus():
|
||||
## for i in range(min(M, N)):
|
||||
## # print i
|
||||
## left.next = intbv(i)
|
||||
## right.next = intbv(i)
|
||||
## yield delay(10)
|
||||
## for i in range(100):
|
||||
## left.next = randrange(M)
|
||||
## right.next = randrange(N)
|
||||
## yield delay(10)
|
||||
## for j, k in ((0, 0), (0, N-1), (M-1, 0), (M-1, N-1)):
|
||||
## left.next = j
|
||||
## right.next = k
|
||||
## yield delay(10)
|
||||
|
||||
## def check():
|
||||
## while 1:
|
||||
## yield left, right
|
||||
## yield delay(1)
|
||||
## # print "%s %s %s %s" % (left, right, Boolor, Boolor_v)
|
||||
## self.assertEqual(Bitand, Bitand_v)
|
||||
## self.assertEqual(Bitor, Bitor_v)
|
||||
## self.assertEqual(Bitxor, Bitxor_v)
|
||||
## self.assertEqual(FloorDiv, FloorDiv_v)
|
||||
## self.assertEqual(LeftShift, LeftShift_v)
|
||||
## self.assertEqual(Modulo, Modulo_v)
|
||||
## self.assertEqual(Mul, Mul_v)
|
||||
## self.assertEqual(RightShift, RightShift_v)
|
||||
## self.assertEqual(Sub, Sub_v)
|
||||
## self.assertEqual(Sum, Sum_v)
|
||||
|
||||
## return augmops, augmops_v, stimulus(), check()
|
||||
M = 2**m
|
||||
N = 2**n
|
||||
|
||||
seqM = tuple([randrange(M) for i in range(NRTESTS)])
|
||||
seqN = tuple([randrange(N) for i in range(NRTESTS)])
|
||||
|
||||
## def testAugmOps(self):
|
||||
## for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
|
||||
## sim = self.augmBench(m, n)
|
||||
## Simulation(sim).run()
|
||||
left = Signal(intbv(0)[m:])
|
||||
right = Signal(intbv(0)[n:])
|
||||
Bitand = Signal(intbv(0)[max(m, n):])
|
||||
Bitor = Signal(intbv(0)[max(m, n):])
|
||||
Bitxor = Signal(intbv(0)[max(m, n):])
|
||||
FloorDiv = Signal(intbv(0)[m:])
|
||||
LeftShift = Signal(intbv(0)[64:])
|
||||
Modulo = Signal(intbv(0)[m:])
|
||||
Mul = Signal(intbv(0)[m+n:])
|
||||
RightShift = Signal(intbv(0)[m:])
|
||||
Sub = Signal(intbv(0)[max(m, n):])
|
||||
Sum = Signal(intbv(0)[max(m, n)+1:])
|
||||
|
||||
augmops = augmOps( Bitand,
|
||||
Bitor,
|
||||
Bitxor,
|
||||
FloorDiv,
|
||||
LeftShift,
|
||||
Modulo,
|
||||
Mul,
|
||||
RightShift,
|
||||
Sub,
|
||||
Sum,
|
||||
left, right)
|
||||
|
||||
def stimulus():
|
||||
for i in range(NRTESTS):
|
||||
left.next = seqM[i]
|
||||
right.next = seqN[i]
|
||||
yield delay(10)
|
||||
## for j, k in ((0, 0), (0, N-1), (M-1, 0), (M-1, N-1)):
|
||||
## left.next = j
|
||||
## right.next = k
|
||||
## yield delay(10)
|
||||
|
||||
|
||||
def check():
|
||||
while True:
|
||||
yield left, right
|
||||
yield delay(1)
|
||||
print Bitand
|
||||
print Bitor
|
||||
print Bitxor
|
||||
# print FloorDiv
|
||||
## print LeftShift
|
||||
# print Modulo
|
||||
print Mul
|
||||
## print RightShift
|
||||
print Sub
|
||||
print Sum
|
||||
|
||||
return augmops, stimulus(), check()
|
||||
|
||||
|
||||
def checkAugmOps(m, n):
|
||||
assert verify(augmBench, m, n) == 0
|
||||
|
||||
## def testAugmOps():
|
||||
## for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
|
||||
## yield checkAugmOps, m, n
|
||||
|
||||
# Simulation(augmBench(4, 4))
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user