From fe7dc3f1eec999e59c9c3b57fe8d121767ebe92a Mon Sep 17 00:00:00 2001 From: jand Date: Mon, 2 Feb 2004 11:40:20 +0000 Subject: [PATCH] plural --- doc/manual/conversion.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/manual/conversion.tex b/doc/manual/conversion.tex index 8d7550ac..6344aaae 100644 --- a/doc/manual/conversion.tex +++ b/doc/manual/conversion.tex @@ -133,7 +133,7 @@ signals, and with \code{yield} statements specifying wait points and resume conditions. Supported resume conditions are a signal edge, a signal change, or a tuple of such conditions. -\subsection{Supported type\label{conv-subset-types}} +\subsection{Supported types\label{conv-subset-types}} The most important restriction regards object types. Verilog is an almost typeless language, while Python is strongly (albeit