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jand 2004-02-02 11:40:20 +00:00
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doc/manual/conversion.tex
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@ -133,7 +133,7 @@ signals, and with \code{yield} statements specifying wait points and resume
conditions. Supported resume conditions are a signal edge, a signal conditions. Supported resume conditions are a signal edge, a signal
change, or a tuple of such conditions. change, or a tuple of such conditions.
\subsection{Supported type\label{conv-subset-types}} \subsection{Supported types\label{conv-subset-types}}
The most important restriction regards object types. Verilog is an The most important restriction regards object types. Verilog is an
almost typeless language, while Python is strongly (albeit almost typeless language, while Python is strongly (albeit