FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity
2,092 Commits 9 Branches 41 Tags
Commit Graph

2092 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Keerthan Jaic
dfd0bf7db8
Create pythonpackage.yml 2020-04-10 20:13:28 +01:00
jdavidberger
c1c17bd605
Add +: verilog operator (#329) 
* Added test which triggers 'Part select expressions must be constant.' error message

* Added ability to make a +: operator

* Removed unnecessary print statement from test

* Changed verify to analyze
 2020-03-14 07:58:49 -05:00
richmorj
6c25cb252a Updating uart_tx example to use @block decorator and new API. (#320) 
* Updating uart_tx example to use @block decorator and new API.

* Removed wildcard import of myhdl.

* Removed unnecessary import myhdl.
 2019-09-14 20:15:56 -05:00
Ahmet Anbar
829f6f94ed Function name is fixed (#318) 2019-08-10 21:32:39 +01:00
Christopher Felton
c3a74de25f incremented revision in init 0.11 2019-05-31 17:24:04 -05:00
Christopher Felton
22de0e0a84 updated the README to reflect the 0.11 release 2019-05-31 16:49:39 -05:00
Christopher Felton
e3a42a6443
Updated docs for 0.11 release (#315) 
* updated docs for 0.11 release

* revert docs back to the myhdl RTD
 2019-05-19 15:21:04 -05:00
Christopher Felton
2f289f987e
Merge pull request #297 from myhdl/jck.docs 
update installation instructions
 2019-05-19 14:58:18 -05:00
Christopher Felton
e37ec45008
Merge pull request #277 from josyb/enum 
enum: added string output for enums in _traceSignals.py
 2019-05-19 14:57:55 -05:00
Christopher Felton
1bcd6930a4
Merge pull request #313 from josyb/Doc 
Slight wording change
 2019-05-12 18:19:11 -05:00
Josy Boelen
cb84c92d92 (pedantic) correction of deprecated 2019-05-11 14:50:17 +02:00
Keerthan Jaic
f8efa3d041
Merge pull request #302 from jck/debug_info 
add simple debug info module
 2019-02-03 20:15:56 -05:00
Keerthan Jaic
9374cc6915 add simple debug info module 2019-02-03 17:39:19 -05:00
Keerthan Jaic
ea716db8d2 update installation instructions 
fixes #295
 2019-02-02 23:25:27 -05:00
Keerthan Jaic
e98d663219
Merge pull request #298 from myhdl/jck.issue_templates 
basic issue templates
 2019-02-02 23:22:13 -05:00
Keerthan Jaic
e25bf37681 basic issue templates 2019-02-02 23:21:38 -05:00
Christopher Felton
f696b82ca5
Merge pull request #275 from rubund/spelling_fixes 
Spelling fixes in documentation
 2019-01-09 06:22:30 -06:00
Christopher Felton
56745dc2a5
Merge pull request #292 from josyb/EKWCD2 
Enhanced VHDL keyword collision detect
 2019-01-09 06:21:57 -06:00
Josy Boelen
197f1d3c9b Nested Top-Level Interfaces (#270) 
* _analyze.py: added top-level conversion of nested Interfaces
tb_inc.v: this commit keeps popping up ...

* Added initial test for conversion of nested interfaces at the top-level

* added conversion in __main__ to allow 'visual' inspection of generated code

* corrected 'renaming'
test_interfaces2.py: added if __name__ == '__main__': section to test locally
test_toplevel_interfaces.py: reworked structure
 2019-01-09 06:16:52 -06:00
Josy Boelen
8a3af6f856 conversion to VHDL: moved validation of port names before assign port_num names in case of 'std_logic_ports=True' 2019-01-04 09:21:03 +01:00
Josy Boelen
e18557760f Enhanced Enhanced VHDL Keyword Collision Check (#285) 
* added clearing of _usednames list at start of conversion

* [ENH] Added tests for checking the VHDL code for picking up invalid names

* added check for double underscore in VHDL names

* corrected (with Henry's help) to run with Python 3.x

* added category=ToVHDLWarning in _nameValid() check

* move test for used VHDL name one level up
added a main i test_keywords.py to run the tests manually (and debug them with print() statements ...)

* corrected invalid_function_underscore to call on invalid_signal_underscore to solicit for a double underscore
 2018-12-06 08:10:08 -06:00
Josy Boelen
b94e67bed0 corrected invalid_function_underscore to call on invalid_signal_underscore to solicit for a double underscore 2018-12-05 20:12:30 +01:00
Josy Boelen
f65826a5a9 move test for used VHDL name one level up 
added a main i test_keywords.py to run the tests manually (and debug them with print() statements ...)
 2018-12-05 20:04:20 +01:00
Josy Boelen
896e050350 added category=ToVHDLWarning in _nameValid() check 2018-12-05 19:47:22 +01:00
Josy Boelen
1c074e8e6f corrected (with Henry's help) to run with Python 3.x 2018-12-05 19:26:21 +01:00
Josy Boelen
43e4190a6a added check for double underscore in VHDL names 2018-12-05 19:18:42 +01:00
Josy Boelen
286b699032 Merge branch 'vhdl_invalid_names_tests' of https://github.com/hgomersall/myhdl into EKWCD2 2018-12-05 17:15:24 +01:00
Henry Gomersall
bf089ac92a
[ENH] Added tests for checking the VHDL code for picking up invalid names 2018-12-05 15:04:41 +00:00
Josy Boelen
0f5006e430 added clearing of _usednames list at start of conversion 2018-12-05 13:32:32 +01:00
Josy Boelen
fd286a5b5f Added VHDL Keyword check for 'enum' member names (#271) 
* Added VHDL Keyword check for 'enum' member names

* removed wild *myhdl* import from _VHDLNameValidation.py

* Trying to break a circular import?

* replaced wild myhdl import in _toVHDL.py by dedicated code

* desperately trying

* disabled _nameValid() to get around circular import of Instantiator

* replaced (Python keyword) *bin* by *tobin*

* Trying with an *empty* __init__.py in the conversion folder

* reworked _toVHDL() method for enum

* forgot to handle *port enum*, factored code
added <if __name__ == '__main__':> conversion code to see the error(s)
 2018-11-12 18:45:56 -06:00
Josy Boelen
a872cd5774 enum: added string output for enums in _traceSignals.py 2018-10-08 21:24:02 +02:00
Christopher Felton
e228402093
Merge pull request #274 from wuerges/master 
Fixed doc: replaced a @instance by a @block.
 2018-10-01 05:14:57 -05:00
Ruben Undheim
715ee56314 Spelling fixes found by Debian lintian 2018-09-30 21:16:42 +02:00
Emilio Wuerges
6c01303a5e
Fixed doc: replaced a @instance by a @block. 2018-09-29 16:42:28 -03:00
Keerthan Jaic
49e90cd21d
Merge pull request #267 from alexforencich/master 
Rename async to isasync to resolve conflict with python 3.7
 2018-08-22 23:50:47 -07:00
Alex Forencich
e30ba4db65 travis: remove py37 from allowed failures 2018-08-20 11:39:03 -07:00
Alex Forencich
dfea638ef3 Rename async to isasync to resolve conflict with python 3.7 2018-08-20 11:37:47 -07:00
Keerthan Jaic
f3c4a3aeee
Merge pull request #269 from jck/travis 
travis fixes
 2018-08-20 01:37:14 -07:00
Keerthan Jaic
280a17b802 travis: add pypy3.5 to allowed failures 2018-08-20 01:34:32 -07:00
Keerthan Jaic
dbac9f786f travis: add py37 to allowed failures 2018-08-20 01:25:36 -07:00
Keerthan Jaic
ec343912e9 travis: switch to pypy3.5 2018-08-20 01:06:29 -07:00
Keerthan Jaic
5907220c53 travis: switch to xenial for py37 2018-08-20 00:55:28 -07:00
Keerthan Jaic
307fc9884a travis: add py37, drop py34 and py35 2018-08-20 00:55:28 -07:00
Keerthan Jaic
eff4db0e3d travis: get ghdl from ppa 2018-08-20 00:55:28 -07:00
Keerthan Jaic
f838b241c1 move dep installs to travis.yml 
also fix ghdl installation
 2018-08-20 00:55:28 -07:00
Jan Decaluwe
160719dd6d version bump 0.10 2018-04-02 09:30:11 +02:00
Jan Decaluwe
8153a3e630 proofread 2018-04-02 09:25:42 +02:00
Jan Decaluwe
bb69f9f481 update 2018-04-01 18:22:50 +02:00
Jan Decaluwe
6104534150 reference update for block 2018-04-01 10:29:07 +02:00
Jan Decaluwe
4973434f5d version number 2018-03-29 17:29:24 +02:00